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AK5351-VF 参数 Datasheet PDF下载

AK5351-VF图片预览
型号: AK5351-VF
PDF下载: 下载PDF文件 查看货源
内容描述: 增强双位20位ADC [Enhanced Dual bit 20bit ADC]
分类和应用: 转换器模数转换器光电二极管
文件页数/大小: 19 页 / 176 K
品牌: AKM [ ASAHI KASEI MICROSYSTEMS ]
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ASAHI KASEI  
[AK5351]  
„ Power-down mode  
The AK5351 has to be reset once by bringing PD "L" upon power-up. All internal registers of the digital filter  
and so on in the AK5351 are reset by this operation. When exiting the power-down mode(PD="H"), the internal  
timing starts clocking by first MCLK ""(rising edge). In master mode internal counter starts at once, in slave  
mode internal counter starts after synchronizing with the first rising edge of LRCK.The serial output data is  
available after 516 counting clock of LRCK cycle.  
„ Asynchronization-reset  
In slave mode, if the phase difference between LRCK and internal control signals is larger than +1/16~-1/16 of  
word period(1/fs), the synchronization of internal control signals with LRCK is done automatically at the first  
rising edge of LRCK.  
„ High Pass Filter(HPFE pin)  
The AK5351 has a Digital High Pass Filter(HPF) for DC-offset cancel. When HPFE pin goes "H", HPF is  
enabled.The cut-off frequency of the HPF is 1Hz(@fs=48kHz). It also scales with the sampling frequency(fs).  
The HPF can be disabled by bringing HPFE pin "L". In this case, the AK5351 has the DC-offset of a few mV.  
0166-E-00  
1997/4  
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