ASAHI KASEI
[AK5351]
SYSTEM DESIGN
Figure 5 shows the system connection diagram. Figure 6 and Figure 7 shows the input buffer circuit. An
evaluation board[AKD5351/2] is available which demonstrates the optimum layout, power supply arrangement
and measurement results.
Figure 5 . System Connection Diagram Example
NOTE: +5V Analog should be powered the same time or earlier than +5V Digital.
Grounding and Power Supply Decoupling
The AK5351 requires careful attention to power supply and grounding arrangements.The VA and VB are
connected together through the chip substrate and have several ohm resistance. The power to VB should
come up at the same time or faster than the power to VD, when they are fed separately to the device (Figure 5).
As to the connections of decoupling capacitors, refer to Figure 5 .The 0.1uF of decoupling capacitors
connected power supply pins should be as near as possible to the power supply pin.
As AIN± pins is near VD pin, ground pattern should be inserted between VD line and AINL± lines to avoid
digital noise coupling. Refer to evaluation board manual of AKD5352/1 Rev.B about board layout.
0166-E-00
1997/4
- 14 -
AKM [ ASAHI KASEI MICROSYSTEMS ]
