ASAHI KASEI
[AK5351]
Serial Data Interface
Audio Serial Interface has four kinds of mode, it can be changed by SMODE1 and SMODE2 pins. Data format
is MSB first, 2's complement.
Figure
SMODE1 SMODE2
Mode
Slave Mode: 20bit, MSB justified
Master Mode: Similar to I2S
Slave Mode: I2S
L/R polarity
Lch=H, Rch=L
Lch=H, Rch=L
Lch=L, Rch=H
Lch=L, Rch=H
Figure 1
Figure 2
Figure 3
Figure 4
L
H
L
L
L
H
H
H
Master Mode: I2S
Table 2 . Serial Interface
1) SLAVE mode
An output channel is defined by LRCK. Both channel data are output in sequence, in order of the Lch first then
Rch at the rate of fs. Data bits are clocked out via the SDATA pin at SCLK rate. Figure 1 and Figure 3 shows
data output timing at SCLK=64fs. FSYNC enables SCLK to start clocking out data. The MSB is clocked out by
the LRCK edge. SCLK causes the ADC to output succeeding bits when FSYNC is high. However, as I2S slave
mode ignores FSYNC, it should hold "L" or "H".
2) MASTER mode
In MASTER mode, the A/D converter is driven from a master clock(MCLK:256fs/384fs) and outputs all other
clocks(LRCK, SCLK).The falling edge of SCLK causes the ADC to output each bit. Figure 2 and Figure 4
shows the output timing. 2x fs clock of 50% duty is output via the FSYNC pin. FSYNC rises one SCLK cycle
after the transition of LRCK edges and stays high during 16 serial clocks(16*tSLK). Upper 16 bit data is output
during FSYNC "H", lower 4 bit is output after FSYNC "L" transition.
Figure 1 . Data Output Timing (Slave mode)
0166-E-00
1997/4
- 11 -
AKM [ ASAHI KASEI MICROSYSTEMS ]
