ASAHI KASEI
SWITCHING CHARACTERISTICS
(Ta=25°C; VA,VD,VB=5.0V±10%; C
L
=20pF)
Parameter
Control Clock Frequency
Master Clock 256fs:
Pulse width Low
Pulse width High
384fs:
Pulse width Low
Pulse width High
Serial Data Output Clock
Channel Select Clock(Sampling Frequency)
Duty Cycle
Serial Interface Timing
(Note 14 )
Slave Mode(SMODE1="L")
SCLK Period
SCLK Pulse width Low
Pulse width High
SCLK Rising to LRCK Edge (Note 15 )
LRCK Edge to SCLK Rising (Note 15 )
LRCK Edge to SDATA MSB Valid
SCLK Falling to SDATA Valid
SCLK Rising to FSYNC Edge(Note 15 )
FSYNC Edge to SCLK Rising(Note 15 )
Master Mode(SMODE1="H")
SCLK Frequency
Duty Cycle
FSYNC Frequency
Duty Cycle
SCLK Falling to LRCK Edge
LRCK Edge to FSYNC Rising
SCLK Falling to SDATA Valid
SCLK Falling to FSYNC Edge
Power down timing
PD Pulse width
PD Rising to SDATA Valid
(Note 16 )
Symbol
f
CLK
t
CLKL
t
CLKH
f
CLK
t
CLKL
t
CLKH
f
SLK
fs
min
2.048
30.0
30.0
3.072
20.0
20.0
8
25
typ
12.288
[AK5351]
max
13.824
Unit
MHz
ns
ns
MHz
ns
ns
MHz
kHz
%
18.432
20.736
3.072
48
6.912
54
75
t
SLK
t
SLKL
t
SLKH
t
SHLR
t
LRSH
t
DLR
t
DSS
t
SHF
t
FSH
f
SLK
f
FSYNC
t
SLR
t
LRF
t
DSS
t
SF
t
PDW
t
PDV
144.7
65
65
30
30
50
50
30
30
64fs
50
2fs
50
-20
1
-20
150
516
50
20
20
ns
ns
ns
ns
ns
ns
ns
ns
ns
Hz
%
Hz
%
ns
tslk
ns
ns
ns
1/fs
Note 14 : Refer to Serial Data Interface.
Note 15 : Specified LRCK and FSYNC edges not to coincide with the rising edges of SCLK.
Note 16 : The number of LRCK rising edges after PD brought high. The value is in master mode.
In slave mode it becomes one LRCK clock(1/fs) longer.
0166-E-00
-8-
1997/4
AKM [ ASAHI KASEI MICROSYSTEMS ]
