[AK4753]
■ PLL Un-Lock
1. PLL Master Mode (PMPLL bit = “1”, M/S bit = “1”)
In this mode, the BICK and LRCK pins go to “L” before the PLL goes to lock state after PMPLL bit = “0” →“1”
(Table 7). After the PLL is locked, a first period of LRCK and BICK may be invalid clock, but these clocks return to
normal state after a period of 1/fs. When sampling frequency is changed, the BICK and LRCK pins do not output
irregular frequency clocks but go to “L” by setting PMPLL bit to “0”.
PLL State
BICK pin
“L” Output
Not fixed
Table 8
LRCK pin
“L” Output
Not fixed
PMPLL bit “0” Æ “1”
PLL Unlock (Except for the above)
PLL Lock
1fs Output
Table 7. Clock Operation at PLL Master Mode (PMPLL bit = “1”, M/S bit = “1”)
■ PLL Master Mode (PMPLL bit = “1”, M/S bit = “1”)
When an external clock (11.2896MHz, 12MHz, 12.288MHz, 22.5792MHz, 24MHz or 24.576MHz) is input to the
XTI/MCKI pin or the crystal oscillator circuit is used, the BICK and LRCK clocks are generated by an internal PLL
circuit. The BICK output frequency is selected between 32fs or 64fs, by BCKO bit (Table 8).
AK4753
11.2896MHz, 12MHz, 12.288MHz
22.5792MHz, 24MHz, 24.576MHz
DSP
MCKI
32fs, 64fs
BCLK
LRCK
BICK
1fs
LRCK
SDTO
SDTI
Figure 20. PLL Master Mode (External Clock Mode)
X’tal
AK4753
11.2896MHz, 12MHz, 12.288MHz
22.5792MHz, 24MHz, 24.576MHz
XTO
DSP
XTI
32fs, 64fs
1fs
BCLK
LRCK
BICK
LRCK
SDTO
SDTI
Figure 21. PLL Master Mode (X’tal Mode)
BCKO bit
BICK Output Frequency
0
1
32fs
64fs
(default)
Table 8. BICK Output Frequency at Master Mode
MS1311-E-00
2011/07
- 22 -
AKM [ ASAHI KASEI MICROSYSTEMS ]
