[AK4753]
■ System Reset
Upon power-up, the AK4753 must be reset by bringing the PDN pin = “L”. This ensures that all internal registers reset
to their initial values. The PDN pin must be set to “L” at power-up.
When PMADC bit is changed from “0” to “1”, the initialization cycle of ADC starts. The ADC outputs settle to data
correspondent to the input signals after the end of initialization. The time from the input of analog signals to the output
of analog signals including the initialization cycle of ADC is 1098/fs=25ms@fs=44.1kHz.
■ Audio Interface Format
Eight types of the data formats are available and are selected by setting the DIF2-0 bits (Table 14). In all modes, the
serial data is MSB first, 2’s complement format. Audio interface formats can be used in both master mode and slave
mode. LRCK and BICK are output from the AK4753 in master mode, but must be input to the AK4753 in slave mode.
DIF2 DIF1
DIF0
bit
Mode
SDTI
LRCK
BICK
Figure
bit
bit
0
1
2
3
4
5
6
7
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
16-bit DSP Mode
16-bit LSB justified
16/20/24-bit MSB justified
16/20/24-bit I2S compatible
20-bit LSB justified
24-bit LSB justified
20-bit DSP Mode
H/L
H/L
H/L
L/H
H/L
H/L
H/L
H/L
Table 15
Figure 31
Figure 33
Figure 34 (default)
Figure 32
Figure 32
Table 16
Table 17
≥32fs
≥32fs
32fs or ≥48fs
32fs or ≥48fs
≥40fs
≥48fs
≥48fs
≥48fs
24-bit DSP Mode
Table 14. Audio Interface Format
In Mode 1/2/3/4/5, the SDTI is latched on the rising edge (“↑”) of BICK.
In Modes 0/6/7 (DSP mode), the audio I/F timing is changed by BCKP and MSBS bits.
When BCKP bit = “0”, the SDTI is latched on the falling edge (“↓”) of BICK.
When BCKP bit = “1”, the SDTI is latched on the rising edge (“↑”) of BICK.
MSBS bit can shift the position of the MSB data of SDTI to the position of the half cycle of the BICK.
MS1311-E-00
2011/07
- 26 -
AKM [ ASAHI KASEI MICROSYSTEMS ]
