[AK4753]
■ System Clock
There are the following four methods to interface with external devices. (Table 1, Table 2)
Mode
PMPLL bit
1
M/S bit
1
PLL3-0 bits
Table 4
Figure
Figure 20
Figure 21
Figure 22
Figure 23
Figure 24
Figure 25
Figure 26
PLL Master Mode
PLL Slave Mode
(PLL Reference Clock: LRCK or BICK pin)
EXT Slave Mode
1
0
0
0
0
1
Table 4
x
x
EXT Master Mode
Table 1. Clock Mode Setting (x: Don’t care)
Mode
XTI/MCKI pin
BICK pin
Output
(Selected by BCKO bit)
LRCK pin
Output
(1fs)
PLL Master Mode
Selected by PLL3-0 bits
PLL Slave Mode
(PLL Reference Clock: LRCK or BICK pin)
Input
Input
(1fs)
Input
(1fs)
Output
(1fs)
GND
(Selected by PLL3-0 bits)
Input
(≥ 32fs)
Output
(Selected by BCKO bit)
EXT Slave Mode
EXT Master Mode
Selected by FS1-0 bits
Selected by FS1-0 bits
Table 2. Clock pins state in Clock Mode
■ Master Mode/Slave Mode
The M/S bit selects either master or slave mode. M/S bit = “1” selects master mode and “0” selects slave mode. When
the AK4753 is in power-down mode (PDN pin = “L”) and when exits reset state, the AK4753 is in slave mode. After
exiting reset state, the AK4753 goes to master mode by changing M/S bit = “1”.
When the AK4753 is in master mode, the LRCK and BICK pins are a floating state until M/S bit becomes “1”. The
LRCK and BICK pins of the AK4753 must be pulled-down or pulled-up by the resistor (about 100kΩ) externally to
avoid the floating state.
M/S bit
Mode
0
1
Slave Mode
Master Mode
(default)
Table 3. Select Master/Slave Mode
MS1311-E-00
2011/07
- 19 -
AKM [ ASAHI KASEI MICROSYSTEMS ]
