[AK4753]
■ PLL Mode (PMPLL bit = “1”)
When PMPLL bit = “1”, the built-in high precision PLL works according to the clock which is set by FS3-0 bits and
PLL3-0 bits. The PLL lock time is shown in Table 4, whenever the AK4753 is supplied to a stable clock after PLL is
powered-up (PMPLL bit = “0” →“1”) or sampling frequency changes.
1. PLL Mode setting
FLT pin
Rp, Cp
PLL Lock
Time
(max)
PLL3 PLL2 PLL1 PLL0 PLL Reference
Input
Frequency
Mode
bit
bit
bit
bit
Clock Input Pin
Cp[F]
Rp[Ω]
10k
10k
10k
10k
10k
10k
10k
10k
10k
0
1
2
3
4
5
6
7
8
0
0
0
0
0
0
0
1
1
0
0
0
1
1
1
1
1
1
0
1
1
0
0
1
1
0
0
0
0
1
0
1
0
1
0
1
LRCK pin
BICK pin
BICK pin
1fs
32fs
64fs
100n
4.7n
4.7n
4.7n
4.7n
4.7n
4.7n
4.7n
4.7n
40 ms
4 ms
4 ms
4 ms
4 ms
4 ms
4 ms
4 ms
4 ms
(default)
XTI/MCKI pin 11.2896MHz
XTI/MCKI pin
XTI/MCKI pin
XTI/MCKI pin
12.288MHz
12MHz
24MHz
XTI/MCKI pin 22.5792MHz
XTI/MCKI pin 24.576MHz
N/A
(*fs: Sampling Frequency, N/A: Not Available)
Table 4. PLL Mode Setting
Others
Others
2. Sampling Frequency setting in PLL Mode
In the case of PLL2 bit = “1”, and the reference clock is input to the XTI/MCKI pin or the crystal oscillator circuit is
used, the sampling frequency can be set according to Table 5.
Mode
FS3 bit
FS2 bit
FS1 bit
FS0 bit
Sampling Frequency
0
1
2
3
4
5
6
7
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
1
1
1
1
0
1
0
1
0
1
0
1
0
1
0
1
8kHz
12kHz
16kHz
24kHz
7.35kHz
11.025kHz
14.7kHz
22.05kHz
32kHz
(default)
10
11
14
15
Others
48kHz
29.4kHz
44.1kHz
N/A
Others
(Reference Clock = XTI/MCKI pin) (N/A: Not Available)
Table 5. Sampling Frequency Setting (PMPLL bit = “1”)
In the case of PLL2 bit = “0” and the reference clock is input to the LRCK or BICK pins, the sampling frequency is set
by FS3 and FS2 bits according to Table 6.
Sampling Frequency
Mode
FS3 bit
FS2 bit
FS1 bit
FS0 bit
Range
0
0
1
0
1
0
x
x
x
0
1
2
x
x
x
(default)
7.35kHz ≤ fs ≤ 12kHz
12kHz < fs ≤ 24kHz
24kHz < fs ≤ 48kHz
N/A
Others
Others
(PLL Reference: Clock: LRCK or BICK pin) (x: Don’t care, N/A: Not Available)
Table 6. Sampling Frequency Setting (PLL2 bit = “0” and PMPLL bit = “1”)
MS1311-E-00
2011/07
- 21 -
AKM [ ASAHI KASEI MICROSYSTEMS ]
