[AK4679]
(2)-2. READ Operations
Set the R/W bit = “1” for the READ operation of the AK4679. After transmission of data, the master can read the next
address’s data by generating an acknowledge instead of terminating the write cycle after the receipt of the first data word.
After receiving each data packet the internal 8-bit address counter is incremented by one, and the next data is
automatically taken into the next address. If the address exceeds AFH prior to generating a stop condition, the address
counter will “roll over” to 00H and the data of 00H will be read out. The AK4679 supports two basic read operations:
CURRENT ADDRESS READ and RANDOM ADDRESS READ.
(2)-2-1. CURRENT ADDRESS READ
The AK4679 contains an internal address counter that maintains the address of the last word accessed, incremented by
one. Therefore, if the last access (either a read or write) were to address “n”, the next CURRENT READ operation would
access data from the address “n+1”. After receipt of the slave address with R/W bit set to “1”, the AK4679 generates an
acknowledge, transmits 1-byte of data to the address set by the internal address counter and increments the internal
address counter by 1. If the master does not generate an acknowledge but instead generates a stop condition, the AK4679
ceases transmission.
S
S
T
O
P
T
A
R
T
R/W="1"
SDAA
SDAE
Slave
Address
S
Data(n)
Data(n+1)
Data(n+2)
Data(n+x)
P
M
A
S
T
E
R
M
A
S
T
E
R
M
A
S
T
E
R
M
A
S
T
E
R
M
A
S
T
E
R
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
N
A
C
K
Figure 128. CURRENT ADDRESS READ
(2)-2-2. RANDOM ADDRESS READ
The random read operation allows the master to access any memory location at random. Prior to issuing the slave address
with the R/W bit “1”, the master must first perform a “dummy” write operation. The master issues a start request, a slave
address (R/W bit = “0”) and then the register address to read. After the register address is acknowledged, the master
immediately reissues the start request and the slave address with the R/W bit “1”. The AK4679 then generates an
acknowledge, 1 byte of data and increments the internal address counter by 1. If the master does not generate an
acknowledge but instead generates a stop condition, the AK4679 ceases transmission.
S
T
A
R
T
S
T
A
R
T
S
T
O
P
R/W="0"
R/W="1"
Slave
Address
Sub *
Address(n)
Slave
Address
S
S
Data(n)
Data(n+1)
Data(n+x)
P
SDAA
M
A
S
T
E
R
M
A
S
T
E
R
M
A
S
T
E
R
M
A
S
T
E
R
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
N
A
C
K
(*: Command code)
Figure 129. RANDOM ADDRESS READ (Audio Block)
R
E
S
T
A
R
T
S
T
A
R
T
S
T
O
P
R/W="0"
R/W="1"
Slave
Address
Command
code
Slave
Address
S
S
Data(n)
Data(n+1)
Data(n+x)
P
Data(n)
SDAE
M
A
S
T
E
R
M
A
S
T
E
R
M
M
A
S
T
E
R
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
N
A
C
K
A
C
K
A
S
T
E
R
Figure 130. RANDOM ADDRESS READ (DSP Block)
MS1402-E-06
2013/02
- 149 -
AKM [ ASAHI KASEI MICROSYSTEMS ]
