[AK4679]
■ SPI Serial Control Interface (DSP block)
DSP block can be controlled by SPI.
1. Configuration
The access format is: Command code (8bit) + Address + Data (MSB First)
Bit Length
Rgister address
or
8
MSB bit is R/W flag. The following 7bits indicate access area such as PRAM/
CRAM/Registers.
Command code
Address to be
accessed
16 or 0
Valid only for those cases where accessed areas have addresses such as PRAM
/CRAM/OFREG. When no address is assigned, there is no data.
Write or Read data
Data
later section
Note 79. SOPCFG bit selects SO output (Hi-z or Low) during CSN = “H”.
CSN
SCLK
don’tcare
(L /H)
X (L/H)
SI
RegAddr,ComCode(8bit)
Data (write)
Address (16bit or 0bit)
Hi-Z
Low
Hi-Z
Low
SO
Data (read)
The output level of SO pin is set by SOCFG bit on CSN pin = “H”.
□ Echo back
The input data of the SI pin is echoed back to the SO pin by shifting 8bit to the right.
1-1. Write Sequence 1
CSN
don’tcare
(L/H)
COMMAND
ADDRESS1
COMMAND
ADDRESS2
ADDRESS1
DATA1
DATA2
DATA1
ADDRESS1
SI
COMMAND
SO HiZ
Low
Hi-Z or Low
ADDRESS2
COMMAND
Figure 135. Echo-Back Writing 1
1-2 Write Sequence 2
CSN
n= ~5
don’t care
(L/H)
Extra 8bit data
DATAn
0xB4
0x00
0x00
DATA1
DATAn
DATA1
SI
HiZ
Low
SO
Hi-Z or Low
COMMAND
ADDRESS1
ADDRESS2
It is possible to verify the written data by inputting extra 8bit clock. If the dummy data is more than the data length, this
dummy data is written on the next address. (24bit for CRAM writing and 16bit for OFREG writing)
Figure 136. Echo-Back Writing 2
MS1402-E-06
2013/02
- 152 -
AKM [ ASAHI KASEI MICROSYSTEMS ]
