[AK4675]
■ Register Definitions (CODEC & SRC Blocks)
Addr Register Name
00H AD/DA Power Management
D7
PMDAR
R/W
D6
PMDAL
R/W
0
D5
D4
D3
PMMICR
D2
PMMICL
D1
D0
PMVCM
PMADR PMADL
R/W
0
PMMP
R/W
0
R/W
Default
R/W
0
R/W
0
R/W
0
R/W
0
0
PMVCM: VCOM Power Management
0: Power down (default)
1: Power up
When any blocks are powered-up, the PMVCM bit must be set to “1”. PMVCM bit can be set to “0” only
when all power management bits are “0”.
PMMP: MPWR pin Power Management
0: Power down: Hi-Z (default)
1: Power up
PMMICL: MIC-Amp Lch Power Management
0: Power down (default)
1: Power up
PMMICR: MIC-Amp Rch Power Management
0: Power down (default)
1: Power up
PMADL: ADC Lch Power Management
0: Power down (default)
1: Power up
When the PMADL or PMADR bit is changed from “0” to “1”, the initialization cycle (1059/fs=24ms
@44.1kHz) starts. After initializing, digital data of the ADC is output.
PMADR: ADC Rch Power Management
0: Power down (default)
1: Power up
PMDAL: DAC Lch Power Management
0: Power down (default)
1: Power up
PMDAR: DAC Rch Power Management
0: Power down (default)
1: Power up
Each block can be powered-down respectively by writing “0” in each bit of this address. When the PDN pin is “L”, all
blocks of CODEC & SRC are powered-down regardless of setting of this address. In this case, register of CODEC &
SRC is initialized to the default value.
When all power management bits are “0”, all blocks of CODEC & SRC are powered-down. The register values of
CODEC & SRC remain unchanged. Power supply current is 20μA(typ) in this case. For fully shut down (typ. 1μA),
PDN pin should be “L”.
When neither ADC nor DAC are used, external clocks may not be present. When ADC or DAC is used, external clocks
must always be present.
MS0963-E-00
2008/05
- 142 -
AKM [ ASAHI KASEI MICROSYSTEMS ]
