[AK4675]
Addr
01H
Register Name
PLL Mode Select 0
R/W
D7
FS3
R/W
1
D6
FS2
R/W
1
D5
FS1
R/W
1
D4
FS0
R/W
1
D3
PLL3
R/W
0
D2
PLL2
R/W
1
D1
PLL1
R/W
1
D0
PLL0
R/W
0
Default
PLL3-0: PLL Reference Clock Select (Table 4)
Default: “0110”(MCKI pin, 12MHz)
FS3-0: Sampling Frequency Select (See Table 5 and Table 6) and MCKI Frequency Select (Table 11)
FS3-0 bits select sampling frequency at PLL mode and MCKI frequency at EXT mode.
Addr Register Name
D7
BTCLK
R/W
0
D6
LP
R/W
0
D5
BCKO
R/W
0
D4
PS1
R/W
0
D3
PS0
R/W
0
D2
MCKO
R/W
0
D1
M/S
R/W
0
D0
PMPLL
02H
PLL Mode Select 1
R/W
R/W
0
Default
PMPLL: PLL Power Management
0: EXT Mode and Power Down (default)
1: PLL Mode and Power up
M/S: Master / Slave Mode Select
0: Slave Mode (default)
1: Master Mode
MCKO: Master Clock Output Enable
0: Disable: MCKO pin = “L” (default)
1: Enable: Output frequency is selected by PS1-0 bits.
PS1-0: MCKO Output Frequency Select (Table 9)
Default: “00”(256fs)
BCKO: BICK Output Frequency Select at Master Mode (Table 10)
LP: Low Power Mode
0: Normal Mode (default)
1: Low Power Mode: available at fs=22.05kHz or less.
BTCLK: Clock Mode of Audio CODEC
0: Synchronized to Audio I/F (default)
1: Synchronized to PCM I/F
BTCLK bit is enabled at only PMPLL bit = “0”. When BTCLK bit is “1”, Audio CODEC and the digital block
(Figure 56) operate by the clock generated by PLLBT.
MS0963-E-00
2008/05
- 143 -
AKM [ ASAHI KASEI MICROSYSTEMS ]
