[AK4675]
(2)-2. READ Operations
Set the R/W bit = “1” for the READ operation of the AK4675. After transmission of data, the master can read the next
address’s data by generating an acknowledge instead of terminating the write cycle after the receipt of the first data word.
After receiving each data packet the internal 7-bit address counter is incremented by one, and the next data is
automatically taken into the next address. In case of CODEC & SRC blocks, if the address exceeds 5AH prior to
generating stop condition, the address counter will “roll over” to 00H and the data of 00H will be read out. In case of
HP/SPK-Amp blocks, if the address exceeds 12H prior to generating stop condition, the address counter will “roll over”
to 00H and the data of 00H will be read out.
The AK4675 supports two basic read operations: CURRENT ADDRESS READ and RANDOM ADDRESS READ.
(2)-2-1. CURRENT ADDRESS READ (except for 10bit SAR ADC Data)
The AK4675 contains an internal address counter that maintains the address of the last word accessed, incremented by
one. Therefore, if the last access (either a read or write) were to address “n”, the next CURRENT READ operation would
access data from the address “n+1”. After receipt of the slave address with R/W bit set to “1”, the AK4675 generates an
acknowledge, transmits 1-byte of data to the address set by the internal address counter and increments the internal
address counter by 1. If the master does not generate an acknowledge to the data but instead generates stop condition, the
AK4675 ceases transmission.
S
S
T
O
P
T
A
R
T
R/W="1"
Slave
Address
S
Data(n)
Data(n+1)
Data(n+2)
Data(n+x)
P
SDA
M
A
S
T
E
R
M
A
S
T
E
R
M
A
S
T
E
R
M
A
S
T
E
R
M
A
S
T
E
R
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
N
A
C
K
Figure 108. CURRENT ADDRESS READ
(2)-2-2. RANDOM ADDRESS READ
The random read operation allows the master to access any memory location at random. Prior to issuing the slave address
with the R/W bit set to “1”, the master must first perform “dummy” write operation. The master issues start request, a
slave address (R/W bit = “0”) and then the register address to read. After the register address is acknowledged, the master
immediately reissues the start request and the slave address with the R/W bit set to “1”. The AK4675 then generates an
acknowledge, 1 byte of data and increments the internal address counter by 1. If the master does not generate an
acknowledge to the data but instead generates a stop condition, the AK4675 ceases transmission.
S
T
A
R
T
S
T
A
R
T
S
T
O
P
R/W="0"
R/W="1"
Slave
Address
Sub
Address(n)
Slave
Address
S
S
Data(n)
Data(n+1)
Data(n+x)
P
SDA
M
A
S
T
E
R
M
A
S
T
E
R
M
A
S
T
E
R
M
A
S
T
E
R
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
N
A
C
K
Figure 109. RANDOM ADDRESS READ
When SAR ADC data is read, register data of Addr=5BH should be read by RANDOM ADDRESS READ, then stop
condition should be input.
S
T
A
R
T
S
T
A
R
T
S
T
O
P
R/W="0"
R/W="1"
Slave
Address
Sub
Address(5BH)
Slave
Address
S
S
Data(D9-2)
Data(D1-0)
P
SDA
A
C
K
A
C
K
A
C
K
M A
M N
A
S
T
A
S
T
C
K
A
C
K
E
R
E
R
Figure 110. RANDOM ADDRESS READ of SAR ADC Data
MS0963-E-00
2008/05
- 138 -
AKM [ ASAHI KASEI MICROSYSTEMS ]
