[AK4675]
■ Speaker Volume (SPGA: Manual Mode)
The speaker volume becomes manual mode when ALCA bit is “0”. This mode is used in the case shown below.
1. After exiting reset state, set-up the registers for ALCA operation (ZTMA1-0, LMTHA and etc).
2. When the registers for ALCA operation (Limiter period, Recovery period and etc) are changed.
For example; when the change of the sampling frequency.
3. When SPGA is used as a manual volume.
SPGA5-0 bits set the gain of the volume control. The SPGA value is changed at zero crossing or timeout. Zero crossing
timeout period is set by ZTMA1-0 bits. In case of OSCN bit = “0”, the write operation to SPGA5-0 bits is prohibited
during 1.6ms after PMSPL or PMSPR bit is set to “1”. In case of OSCN bit = “1”, the write operation to SPGA5-0 bits is
prohibited during the power-up time of the speaker volume block (Table 91) after PMSPL or PMSPR bit is set to “1”. The
speaker volume is powered-up as the default value (0dB) regardless of the setting of SPKG5-0 bits.
SPGA5-0
3FH
3EH
3DH
3CH
:
GAIN (dB)
+19.5
+19.0
+18.5
+18.0
:
Step
19H
18H
17H
:
+0.5
0.0
−0.5
:
0.5dB
(default)
02H
01H
00H
−11.0
−11.5
−12.0
Table 89. Speaker-Amp Volume Setting
When writing to the SPGA5-0 bits continuously, the control register should be written in an interval more than zero
crossing timeout.
ALCA bit
ALCA Status
SPGA5-0 bits
Internal SPGA
Disable
Enable
3CH(+18dB)
Disable
3CH(+18dB)
3CH(+18dB) --> 19H(+0.5dB)
3CH(+18dB)
(1)
(2)
Figure 84. SPGA value during ALCA operation
(1) ALCA operation starts from the SPGA value when ALCA bit is changed to “1”.
(2) Writing to SPGA registers is ignored during ALCA operation. After ALCA is disabled, the SPGA changes to the last
written data by twice period of zero crossing or timeout. When ALCA is enabled again, ALCA bit should be set to
“1” in an interval more than zero crossing timeout period after ALCA bit = “0”.
MS0963-E-00
2008/05
- 116 -
AKM [ ASAHI KASEI MICROSYSTEMS ]
