[AK4675]
■ Speaker-ALC Operation
The ALC (Automatic Level Control) operation of speaker-amp output is executed by ALCA block when ALCA bit = “1”.
When ALCA bit is “0”, the speaker volume depends on the setting value of SPGA5-0 bits.
(1) ALC Limiter Operation
During ALCA limiter operation, when either Lch or Rch exceeds the ALCA limiter detection level (LMTHA bit), the
SPGA value (same value for Lch and Rch) is attenuated automatically by the ALCA limiter ATT step (LMATA1-0 bits).
When ZELMNA bit is set to “0” (zero crossing detection is enabled), the SPGA value is changed by ALCA limiter
operation at the individual zero crossing points of Lch and Rch or at the zero crossing timeout. ZTMA1-0 bits set the zero
crossing timeout period of both ALCA limiter and recovery operation.
When ZELMNA bit = “1” (zero crossing detection is disabled), SPGA value is immediately changed by ALCA limiter
operation. The changing period is typ. 125μs and max. 200μs at OSCN bit = “0”, 256/MCKIA (=125μs
@MCKIA=2.048MHz at OSCN bit = “1” & MSEL bit = “0”, 384/MCKIA (= 125μs @MCKI=3.072MHz) at OSCN bit
= “1” & MSEL bit = “1”. Attenuation step is fixed to 1 step regardless of the setting of LMATA1-0 bits.
The attenuate operation is executed continuously until the input signal level becomes ALCA limiter detection level or
less. After completing the attenuation operation, unless ALCA bit is changed to “0”, the operation repeats when the input
signal level exceeds LMTHA bit.
LMTHA
ALCA Limiter Detection
Level
ALCA Recovery Waiting Counter Reset Level
0
1
(default)
ALCA Output ≥ −7.5dBV
ALCA Output ≥ −11.5dBV
−7.5dBV > ALCA Output ≥ −9.5dBV
−11.5dBV > ALCA Output ≥ −13.5dBV
Note: ALCA limiter detection level and ALCA recovery waiting counter reset level do not
depend on operation voltage.
Table 82. ALCA Limiter Detection Level / Recovery Counter Reset Level (2.0Vpp = −3dBV)
ZELMNA LMATA1 LMATA0
ALCA Limiter ATT Step
0
0
1
1
x
0
1
0
1
x
1 step
2 step
4 step
8 step
1step
0.5dB
1.0dB
2.0dB
4.0dB
0.5dB
(default)
0
1
Table 83. ALCA Limiter ATT Step (x: Don’t’ care)
Zero Crossing Timeout
ZTMA1
ZTMA0
OSCN bit = “0”
OSCN bit = “1”
typ.
max
MSEL bit= “0”
32768/MCKIA
65536/MCKIA
131072/MCKIA 196608/MCKIA
262144/MCKIA 393216/MCKIA
MSEL bit = “1”
49152/MCKIA
98304/MCKIA (default)
0
0
1
1
0
1
0
1
16.4ms
32.8ms
65.6ms
131.2ms
26.3ms
51.5ms
105.0ms
210.0ms
Table 84. ALCA Zero Crossing Timeout Period
MS0963-E-00
2008/05
- 112 -
AKM [ ASAHI KASEI MICROSYSTEMS ]
