[AK4675]
■ Full-differential Mono Line Output (LOP/LON pins)
When LODIF bit = “1”, LOUT3/ROUT3 pins become LOP/LON pins, respectively. Lch/Rch signal of DAC or
LIN1/RIN1/LIN2/RIN2/LIN3/RIN3/LIN4/RIN4 is output from the LOP/LON pins which is full-differential as (L+R)
signal. The load impedance is 10kΩ (min) for the LOP and LON pins, respectively. When the PMLO3 = PMRO3 bits =
“0”, the mono line output enters power-down mode and the output is pulled-down to VSS1. When the PMLO3 = PMRO3
bits = “1” and LOPS3 bit = “1”, mono line output enters power-save mode. Pop noise at power-up/down can be reduced
by changing PMLO3 and PMRO3 bits at LOPS3 bit = “0”. When PMLO3 = PMRO3 bits = “1” and LOPS3 bit = “0”,
mono line output enters in normal operation. L3VL1-0 bits set the volume of mono line output.
L3VL1-0
3H
Attenuation
+9dB
2H
+6dB
(default)
1H
+3dB
0H
0dB
Table 73. Mono Line Output Gain Setting
LOPS3
0
PMLO3/RO3
Mode
LOP/LON pins
0
1
0
1
Power-down
Normal Operation
Power-save
Pull-down to VSS1
Normal Operation
Fall down to VSS1
Rise up to VCOM
(default)
1
Power-save
Table 74. Mono Line Output Mode Setting (x: Don’t care)
<Full-differential Mono Line Output Control Sequence (in case of using Pop Noise Reduction
Circuit)>
(2 )
(5 )
P M L O 3 b it
P M R O 3 b it
(1 )
(3 )
(4 )
(6 )
L O P S 3 b it
L O P , L O N p in s
N o rm a l O u tp u t
≥ 3 0 0 m s
≥ 3 0 0 m s
Figure 77. Mono Line Output 3 Control Sequence (when using Pop Noise Reduction Circuit)
(1) Set LOPS3 bit = “1”. Mono line output enters the power-save mode.
(2) Set PMLO3 = PMRO3 bits = “1”. Mono line output exits the power-down mode.
The LOP and LON pins rise up to VCOM voltage. Rise time is 200ms (max 300ms) at C=1μF and
AVDD=3.3V.
(3) Set LOPS3 bit = “0” after LOP and LON pins rise up. Mono line output exits the power-save mode.
Mono line output is enabled.
(4) Set LOPS3 bit = “1”. Mono line output enters power-save mode.
(5) Set PMLO3 = PMRO3 bits = “0”. Mono line output enters power-down mode.
The LOP and LON pins fall down to VSS1. Fall time is 200ms (max 300ms) at C=1μF and AVDD=3.3V.
(6) Set LOPS3 bit = “0” after LOP and LON pins fall down. Mono line output exits the power-save mode.
MS0963-E-00
2008/05
- 105 -
AKM [ ASAHI KASEI MICROSYSTEMS ]
