[AK4675]
■ Stereo Line Output 3 (LOUT3/ROUT3 pins)
When DACSL and DACSR bits are “1”, Lch/Rch signal of DAC is output from the LOUT3/ROUT3 pins which is
single-ended. When DACSL and DACSR bits are “0”, output signal is muted and LOUT3/ROUT3 pins output VCOM
voltage. The load impedance is 10kΩ (min.). When the PMLO3=PMRO3=LOPS3 bits = “0”, LOUT3/ROUT3 enters
power-down mode and the output is pulled-down to VSS1 by 100kΩ(typ). When the LOPS3 bit is “1”, LOUT3/ROUT3
enters power-save mode. Pop noise at power-up/down can be reduced by changing PMLO3 and PMRO3 bits at LOPS3
bit = “1”. In this case, output signal line should be pulled-down to VSS1 by 20kΩ after AC coupled as Figure 64. Rise/Fall
time is 300ms(max) at C=1μF and AVDD=3.3V. When PMLO3=PMRO3 bits = “1” and LOPS3 bit = “0”,
LOUT3/ROUT3 is in normal operation.
L3VL3-0 bits control the volume of LOUT3/ROUT3.
When LOM3 bit = “1”, DAC output signal is output to LOUT3 and ROUT3 pins as (L+R) mono signal.
When LOOPM3 bit = “1”, the MIC-Amp signal is output to LOUT3 and ROUT3 pins as (L+R) mono signal.
LOPS3
0
PMLO3
Mode
LOUT3 pin
0
1
0
1
Power-down
Normal Operation
Power-save
Pull-down to VSS1
Normal Operation
Fall down to VSS1
Rise up to VCOM
(default)
(default)
1
Power-save
Table 70. Stereo Line Output Mode Select (LOUT3)
LOPS3
0
PMRO3
Mode
ROUT3 pin
0
1
0
1
Power-down
Normal Operation
Power-save
Pull-down to VSS1
Normal Operation
Fall down to VSS1
Rise up to VCOM
1
Power-save
Table 71. Stereo Line Output Mode Select (ROUT3)
L3VL1
L3VL0
Attenuation
+3dB
1
1
0
0
1
0
1
0
0dB
−3dB
−6dB
(default)
Table 72. Stereo Line Output Volume Setting
LOUT3
ROUT3
1μF
220Ω
20kΩ
Figure 73. External Circuit for Stereo Line Output (when using Pop Noise Reduction Circuit)
MS0963-E-00
2008/05
- 101 -
AKM [ ASAHI KASEI MICROSYSTEMS ]
