[AK4675]
LINL1 bit
LINL2 bit
LINL3 bit
LINL4 bit
LOOPL bit
+6/0/−6dB
+6/0/−6dB
+6/0/−6dB
+6/0/−6dB
+6/0/−6dB
IN1+/− pins
IN2+/− pins
IN3+/− pins
IN4+/− pins
RCP/RCN pins
L1VL2-0 bits
MIC-Amp Lch
MIC-Amp Rch
LOOPR bit
M
I
+6/0/−6dB
DACL bit
DACR bit
X
DATT
Stereo DAC Lch
0dB
0dB
DATT
Stereo DAC Rch
Figure 70. Receiver Mixing Circuit (MDIF1=MDIF2=MDIF3=MDIF4 bits = “1”)
■ Stereo Line Output 2 (LOUT2S/ROUT2S pins)
Power supply voltage for the LOUT2S/ROUT2S is supplied from the AVDD pin and centered on the 0.5 x AVDD (typ)
voltage. The load resistance is 25kΩ (min).
When LOM2 bit = “1”, DAC output signal is output to LOUT2S and ROUT2S pins as (L+R) mono signal.
When LOOPM2 bit = “1”, the MIC-Amp signal is output to LOUT2S and ROUT2S pins as (L+R) mono signal.
When PMLO2S and PMRO2S bits are “0”, the LOUT2S/ROUT2S is powered-down, and the outputs (LOUT2S and
ROUT2S pins) go to “L” (VSS1).
MS0963-E-00
2008/05
- 98 -
AKM [ ASAHI KASEI MICROSYSTEMS ]
