[AK4646]
■ Speaker Output
Power supply for Speaker-Amp (SVDD) is 2.2V to 4.0V. In case of dynamic (electromagnetic) speaker (load resistance <
50Ω), SVDD is 2.2V to 3.6V.
Speaker Type
Load Resistance (min)
Load Capacitance (max)
Dynamic Speaker
Piezo (Ceramic) Speaker
50Ω (Note 20)
8Ω
30pF
3μF (Note 20)
Note 20. Load impedance is total impedance of series resistance and piezo speaker impedance at 1kHz in 38HFigure 34.
Load capacitance is capacitance of piezo speaker. When piezo speaker is used, 10Ω or more series resistors
should be connected at both SPP and SPN pins, respectively.
Table 42. Speaker Type and Power Supply Range
The DAC output signal is input to the Speaker-amp as [(L+R)/2]. The Speaker-amp is mono and BTL output. The gain is
set by SPKG1-0 bits. Output level depends on AVDD voltage and SPKG1-0 bits.
Gain
SPKG1-0 bits
ALC2 bit = “0”
+4.6dB
ALC2 bit = “1”
+6.6dB
00
01
10
11
(default)
+6.6dB
+8.6dB
+10.6dB
+8.6dB
+10.6dB
+12.6dB
Table 43. SPK-Amp Gain
SPK-Amp Output (DAC Input = 0dBFS)
SPKG1-0 bits
ALC2 bit = “0”
ALC2 bit = “1”
(LMTH1-0 bits = “00”)
00
01
10
11
3.37Vpp
3.17Vpp
4.00Vpp
5.04Vpp (Note 40)
6.33Vpp (Note 40)
4.23Vpp (Note 40)
5.33Vpp (Note 40)
6.71Vpp (Note 40)
Note 40. The output level is calculated by assuming that output signal is not clipped. In actual case, output signal may be
clipped when DAC outputs 0dBFS signal. DAC output level should be set to lower level by setting digital
volume so that Speaker-Amp output level is 4.0Vpp or less and output signal is not clipped.
Table 44. SPK-Amp Output Level
MS0557-E-05
2011/01
- 49 -
AKM [ ASAHI KASEI MICROSYSTEMS ]
