[AK4646]
■ Stereo Line Output (LOUT/ROUT pins)
When DACL bit is “1”, Lch/Rch signal of DAC is output from the LOUT/ROUT pins which is single-ended. When
DACL bit is “0”, output signal is muted and LOUT/ROUT pins output VCOM voltage. The load impedance is 10kΩ
(min.). When the PMLO bit = LOPS bit = “0”, the stereo line output enters power-down mode and the output is
pulled-down to AVSS by 100kΩ(typ). When the LOPS bit is “1”, stereo line output enters power-save mode. Pop noise at
power-up/down can be reduced by changing PMLO bit at LOPS bit = “1”. In this case, output signal line should be
pulled-down to AVSS by 20kΩ after AC coupled as Figure 32. Rise/Fall time is 300ms (max) at C=1μF. When PMLO bit
= “1” and LOPS bit = “0”, stereo line output is in normal operation.
LOVL bit set the gain of stereo line output.
“DACL”
“LOVL”
LOUT pin
ROUT pin
DAC
Figure 31. Stereo Line Output
LOPS
0
PMLO
Mode
LOUT/ROUT pin
Pull-down to AVSS
Normal Operation
Fall down to AVSS
Rise up to VCOM
0
1
0
1
Power-down
Normal Operation
Power-save
(default)
1
Power-save
Table 40. Stereo Line Output Mode Select (x: Don’t care)
LOVL1-0 bits
Gain
0dB
+2dB
+4dB
+6dB
00
01
10
11
(default)
Table 41. Stereo Line Output Volume Setting
LOUT
ROUT
1μF
220Ω
20kΩ
Figure 32. External Circuit for Stereo Line Output (in case of using Pop Reduction Circuit)
MS0557-E-05
2011/01
- 47 -
AKM [ ASAHI KASEI MICROSYSTEMS ]
