ASAHI KASEI
[AK4645]
EXT Slave Mode (PMPLL bit = “0”, M/S bit = “0”)
When PMPLL bit is “0”, the AK4645 becomes EXT mode. Master clock is input from MCKI pin, the internal PLL circuit
is not operated. This mode is compatible with I/F of the normal audio CODEC. The clocks required to operate are MCKI
(256fs, 512fs or 1024fs), LRCK (fs) and BICK (≥32fs). The master clock (MCKI) should be synchronized with LRCK.
The phase between these clocks does not matter. The input frequency of MCKI is selected by FS1-0 bits (see Table 12).
MCKI Input
Frequency
Sampling Frequency
Range
Mode
FS3-2 bits
FS1 bit
FS0 bit
Don’t care
Don’t care
Don’t care
Don’t care
0
1
2
3
0
0
1
1
0
1
0
1
256fs
1024fs
256fs
512fs
Default
7.35kHz ∼ 48kHz
7.35kHz ∼ 13kHz
7.35kHz ∼ 48kHz
7.35kHz ∼ 26kHz
Table 12. MCKI Frequency at EXT Slave Mode (PMPLL bit = “0”, M/S bit = “0”)
The S/N of the DAC at low sampling frequencies is worse than at high sampling frequencies due to out-of-band noise.
The out-of-band noise can be improved by using higher frequency of the master clock. The S/N of the DAC output
through LOUT/ROUT pins at fs=8kHz is shown in Table 13.
S/N
MCKI
(fs=8kHz, 20kHzLPF + A-weighted)
256fs
512fs
1024fs
83dB
93dB
93dB
Table 13. Relationship between MCKI and S/N of LOUT/ROUT pins
The external clocks (MCKI, BICK and LRCK) should always be present whenever the ADC or DAC is in operation
(PMADL bit = “1”, PMADR bit = “1” or PMDAC bit = “1”). If these clocks are not provided, the AK4645 may draw
excess current and it is not possible to operate properly because utilizes dynamic refreshed logic internally. If the external
clocks are not present, the ADC and DAC should be in the power-down mode (PMADL=PMADR=PMDAC bits = “0”).
AK4645
MCKO
DSP or µP
256fs, 512fs or 1024fs
MCKI
BICK
LRCK
MCLK
BCLK
LRCK
≥ 32fs
1fs
SDTI
SDTO
SDTI
SDTO
Figure 23. EXT Slave Mode
MS0543-E-00
2006/09
- 30 -
AKM [ ASAHI KASEI MICROSYSTEMS ]
