ASAHI KASEI
[AK4645]
System Reset
Upon power-up, the AK4645 should be reset by bringing the PDN pin = “L”. This ensures that all internal registers reset
to their initial values.
The ADC enters an initialization cycle that starts when the PMADL or PMADR bit is changed from “0” to “1” at PMDAC
bits is “0”. The initialization cycle time is 1059/fs=24ms@fs=44.1kHz. During the initialization cycle, the ADC digital
data outputs of both channels are forced to a 2’s compliment, “0”. The ADC output reflects the analog input signal after
the initialization cycle is complete. When PMDAC bit is “1”, the ADC does not require an initialization cycle.
The DAC enters an initialization cycle that starts when the PMDAC bit is changed from “0” to “1” at PMADL and
PMADR bits are “0”. The initialization cycle time is 1059/fs=24ms@fs=44.1kHz. During the initialization cycle, the
DAC input digital data of both channels are internally forced to a 2’s compliment, “0”. The DAC output reflects the
digital input data after the initialization cycle is complete. When PMADL or PMADR bit is “1”, the DAC does not require
an initialization cycle.
Audio Interface Format
Four types of data formats are available and are selected by setting the DIF1-0 bits (seeTable 17). In all modes, the serial
data is MSB first, 2’s complement format. Audio interface formats can be used in both master and slave modes. LRCK
and BICK are output from the AK4645 in master mode, but must be input to the AK4645 in slave mode.
Mode
DIF1 bit
DIF0 bit
SDTO (ADC)
DSP Mode
MSB justified
MSB justified
I2S compatible
SDTI (DAC)
DSP Mode
LSB justified
MSB justified
I2S compatible
BICK
≥ 32fs
≥ 32fs
≥ 32fs
≥ 32fs
Figure
0
1
2
3
0
0
1
1
0
1
0
1
Table 18
Figure 29
Figure 30
Figure 31
Default
Table 17. Audio Interface Format
In modes 1, 2 and 3, the SDTO is clocked out on the falling edge (“↓”) of BICK and the SDTI is latched on the rising edge
(“↑”).
In Modes 0 (DSP mode), the audio I/F timing is changed by BCKP and MSBS bits (Table 18).
DIF1 DIF0 MSBS BCKP
Audio Interface Format
Figure
MSB of SDTO is output by the rising edge (“↑”) of the first
BICK after the rising edge (“↑”) of LRCK.
MSB of SDTI is latched by the falling edge (“↓”) of the BICK
just after the output timing of SDTO’s MSB.
MSB of SDTO is output by the falling edge (“↓”) of the first
BICK after the rising edge (“↑”) of LRCK.
MSB of SDTI is latched by the rising edge (“↑”) of the BICK
just after the output timing of SDTO’s MSB.
MSB of SDTO is output by next rising edge (“↑”) of the falling
edge (“↓”) of the first BICK after the rising edge (“↑”) of LRCK.
MSB of SDTI is latched by the falling edge (“↓”) of the BICK
just after the output timing of SDTO’s MSB.
MSB of SDTO is output by next falling edge (“↓”) of the rising
edge (“↑”) of the first BICK after the rising edge (“↑”) of LRCK.
MSB of SDTI is latched by the rising edge (“↑”) of the BICK
just after the output timing of SDTO’s MSB.
0
0
1
1
0
1
0
1
Figure 25 Default
Figure 26
Figure 27
Figure 28
0
0
Table 18. Audio Interface Format in Mode 0
If 16-bit data that ADC outputs is converted to 8-bit data by removing LSB 8-bit, “−1” at 16bit data is converted to “−1”
at 8-bit data. And when the DAC playbacks this 8-bit data, “−1” at 8-bit data will be converted to “−256” at 16-bit data
and this is a large offset. This offset can be removed by adding the offset of “128” to 16-bit data before converting to 8-bit
data.
MS0543-E-00
2006/09
- 32 -
AKM [ ASAHI KASEI MICROSYSTEMS ]
