[AK4627]
■ ADC partial Power-Down Function
All of the ADCs can be powered-down individually by PDAD2-1 bits. The analog part and the digital part of the ADC are
in power-down mode when the PDAD2-1 bits = “1”. The analog section of ADCs are initialized after exiting the
power-down state. Digital outputs corresponding to analog inputs have group delay (GD). ADC outputs “0” data in
power-down state. Click noise occurs when the internal RSTN bit becomes “1”. Mute the digital output externally if the
click noise influences system applications. Figure 19 shows the power-down and power-up sequences by PDAD2-1 bits.
PDAD2-1 bit
Power Down Channel
ADCDigital
Normal Operation
Power-down
Power-down
Power-down
Normal Operation
516/fs (1)
Init Cycle
Normal Operation
Internal State
516/fs (1)
Init Cycle
ADC Analog
Internal State
Normal Operation
GD
Normal Operation Power-down
Normal Operation
(2)
GD
(2)
ADC In
(Analog)
(3)
“0”data
ADC Out
(Digital)
(4)
(4)
Normal Operation Channel
(2)
(2)
GD
GD
ADC In
(Analog)
(3)
“0”data
ADC Out
(Digital)
Clock In
MCLK,LRCK,SCLK
Note:
(1) The analog part of the ADC is initialized after exiting reset state.
(2) Analog outputs corresponding to the digital inputs have group delay (GD).
(3) ADC outputs “0” data in power-down state.
(4) Click noise occurs when the internal RSTN bit becomes “1”. Mute the digital output externally if the click noise
influences system applications.
Figure 19. ADC partial power-down example
MS1278-E-02
2012/03
- 29 -
AKM [ ASAHI KASEI MICROSYSTEMS ]
