[AK4627]
■ Power-Down
The ADC and DACs of AK4627 are placed in the power-down mode by bringing the PDN “L” and both digital filters are
reset at the same time. Bringing the PDN pin=“L” also resets the control registers to their default values. In the
power-down mode, the analog outputs become to VCOM voltage and DZF1-2 pins output “L”. This reset should always
be made after power-up. In case of ADC, an analog initialization cycle starts after exiting the power-down mode.
Therefore, the output data, SDTO1-2 become available after 516 cycles of LRCK clock. In case of the DAC, an analog
initialization cycle starts after exiting the power-down mode. The analog outputs are VCOM voltage during the
initialization. Figure 16 shows the power-down/up sequences.
All ADCs and all DACs can be powered-down by PWADN and PWDAN bits respectively. DAC1-3 can be power-down
individually by PDDA1-3 bits. In this case, the internal register values are not initialized. When PWADN bit= “0” and
PDAD1-2 bits = “0”, SDTO1-2 become “L”. When PWDAN bit = “0” and PDDA1-3 bits= “0”, the analog outputs go to
VCOM voltage and DZF1-2 pins go to “H”. As some click noise occurs, the analog output should be muted externally if
the click noise influences system applications.
PDN
(1)
516/fs
ADC Internal
State
Normal Operation
Power-down
Power-down
Init Cycle
512/fs
Normal Operation
(2)
DAC Internal
State
Normal Operation
GD
Init Cycle
Normal Operation
GD
(3)
ADC In
(Analog)
(4)
ADC Out
(Digital)
(5)
“0”data
DAC In
(Digital)
“0”data
(3)
GD
GD
(6)
(6)
DAC Out
(Analog)
(7)
Clock In
MCLK,LRCK,SCLK
Don’t care
10∼11/fs (10)
(8)
DZF1/DZF2
External
Mute
(9)
Mute ON
Notes:
(1) The analog part of ADC is initialized after exiting the power-down state.
(2) The analog part of DAC is initialized after exiting the power-down state.
(3) Digital outputs corresponding to analog inputs and analog outputs corresponding to digital inputs have group delay
(GD).
(4) ADC outputs “0” data in power-down state.
(5) Click noise occurs at the end of initialization of the analog part. Mute the digital output externally if the click noise
influences system application.
(6) Click noise occurs at the falling edge of PDN and at 512/fs after the rising edge of PDN.
(7) When the external clocks (MCLK, BICK and LRCK) are stopped, the AK4627 should be in the power-down mode.
(8) DZF pins are “L” in power-down mode (PDN pin= “L”).
(9) Mute the analog output externally if the click noise (6) influences system application.
(10) DZF1-2 pins are “L” for 10∼11/fs after PDN = “↑”.
Figure 16. Power-down/up sequence example
MS1278-E-02
2012/03
- 26 -
AKM [ ASAHI KASEI MICROSYSTEMS ]
