[AK4614]
1/fCLK
VIH
VIL
MCKI
tCLKH
tCLKL
1/fMCK
MCKO
50%TVDD1
tdMCKH
tdMCKL
dMCK
= tdMCKH (or tdMCKL) x fMCK x 100
1/fs
LRCK
50%TVDD1
tdLRKH
tdLRKL
dLRK
= tdLRKH (or tdLRKL) x fs x 100
1/fBCK
50%TVDD1
BICK
tdBCKH
tdBCKL
dBCK
= tdBCKH (or tdBCKL) x fs x 100
Figure 5. Clock Timing (TDM1/0 bit = “00” & Master mode)
1/fCLK
VIH
VIL
MCKI
tCLKH
tCLKL
1/fMCK
MCKO
50%TVDD1
tdMCKH
tdMCKL
dMCK
= tdMCKH (or tdMCKL) x fMCK x 100
1/fs
LRCK
50%TVDD1
tLRH
1/fBCK
50%TVDD1
BICK
tdBCKH
tdBCKL
dBCK
= tdBCKH (or tdBCKL) x fs x 100
Figure 6. Clock Timing (Except TDM1/0 bit = “00” & Master mode)
MS1025-E-00
2008/10
- 21 -
AKM [ ASAHI KASEI MICROSYSTEMS ]
