[AK4614]
Parameter
Symbol
min
typ
max
Units
Audio Interface Timing (Master mode)
Stereo mode (TDM0 bit = “0”, TDM1 bit = “0”)
(TVDD1= 1.6V∼3.6V)
BICK Frequency
BICK Duty
BICK “↓” to LRCK
BICK “↓” to SDTO
SDTI Hold Time
-
-
fBCK
dBCK
tMBLR
tBSD
tSDH
tSDS
64fs
50
-
-
-
-
-
40
70
-
Hz
%
ns
ns
ns
ns
−40
−70
50
50
-
-
SDTI Setup Time
(TVDD1= 3.0V∼3.6V)
BICK Frequency
BICK Duty
BICK “↓” to LRCK
BICK “↓” to SDTO
SDTI Hold Time
-
-
fBCK
dBCK
tMBLR
tBSD
tSDH
tSDS
64fs
50
-
-
-
-
-
23
23
-
Hz
%
ns
ns
ns
ns
−23
−23
10
10
-
-
SDTI Setup Time
TDM512 mode (TDM0 bit = “0”, TDM1 bit = “1”)
(TVDD1= 3.0V∼3.6V)
BICK Frequency
BICK Duty
BICK “↓” to LRCK
SDTO Setup time BICK “↑”
SDTO Hold time BICK “↑”
SDTI Hold Time
(Note 17)
fBCK
dBCK
tMBLR
tBSS
tBSH
tSDH
tSDS
-
-
512fs
50
-
-
10
-
-
-
Hz
%
-10
6
5
10
10
ns
ns
ns
ns
ns
-
-
-
-
-
SDTI Setup Time
TDM256 mode (TDM0 bit = “1”, TDM1 bit = “0”)
(TVDD1= 3.0V∼3.6V)
BICK Frequency
BICK Duty
BICK “↓” to LRCK
SDTO Setup time BICK “↑”
SDTO Hold time BICK “↑”
SDTI Hold Time
(Note 18)
-
-
fBCK
dBCK
tMBLR
tBSS
tBSH
tSDH
tSDS
256fs
50
-
-
-
-
-
10
-
-
-
Hz
%
ns
ns
ns
ns
ns
−10
6
5
10
10
-
-
-
SDTI Setup Time
TDM128 mode (TDM0 bit = “1”, TDM1 bit = “1”)
(TVDD1= 3.0V∼3.6V)
BICK Frequency
BICK Duty
BICK “↓” to LRCK
SDTO Setup time BICK “↑”
SDTO Hold time BICK “↑”
SDTI Hold Time
(Note 19)
-
-
fBCK
dBCK
tMBLR
tBSS
tBSH
tSDH
tSDS
128fs
50
-
-
-
-
-
10
-
-
-
Hz
%
ns
ns
ns
ns
ns
−10
6
5
10
10
-
-
-
SDTI Setup Time
Note 21. BICK rising edge must not occur at the same time as LRCK edge.
MS1025-E-00
2008/10
- 18 -
AKM [ ASAHI KASEI MICROSYSTEMS ]
