[AK4614]
Parameter
Symbol
min
typ
max
Units
Audio Interface Timing (Slave mode)
Stereo mode (TDM0 bit = “0”, TDM1 bit = “0”)
(TVDD1= 1.6V∼3.6V)
BICK Period
tBCK
tBCKL
tBCKH
tLRB
tBLR
tLRS
tBSD
tSDH
tSDS
324
130
130
20
ns
ns
ns
ns
ns
ns
ns
ns
ns
BICK Pulse Width Low
Pulse Width High
LRCK Edge to BICK “↑”
BICK “↑” to LRCK Edge
(Note 21)
(Note 21)
20
LRCK to SDTO(MSB) (Except I2S mode)
BICK “↓” to SDTO
80
80
SDTI Hold Time
50
50
SDTI Setup Time
(TVDD1= 3.0V∼3.6V)
BICK Period
BICK Pulse Width Low
Pulse Width High
tBCK
tBCKL
tBCKH
tLRB
tBLR
tLRS
tBSD
tSDH
tSDS
81
33
33
23
23
ns
ns
ns
ns
ns
ns
ns
ns
ns
LRCK Edge to BICK “↑”
BICK “↑” to LRCK Edge
(Note 21)
(Note 21)
LRCK to SDTO(MSB) (Except I2S mode)
BICK “↓” to SDTO
23
23
SDTI Hold Time
SDTI Setup Time
10
10
TDM512 mode (TDM0 bit = “0”, TDM1 bit = “1”)
(TVDD1= 3.0V∼3.6V)
(Note 17)
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
BICK Period
tBCK
tBCKL
tBCKH
tLRB
tBLR
tBSS
tBSH
tSDH
tSDS
40
16
16
10
10
6
5
10
10
BICK Pulse Width Low
Pulse Width High
LRCK Edge to BICK “↑”
BICK “↑” to LRCK Edge
SDTO Setup time BICK “↑”
SDTO Hold time BICK “↑”
SDTI Hold Time
(Note 21)
(Note 21)
SDTI Setup Time
TDM256 mode (TDM0 bit = “1”, TDM1 bit = “0”)
(TVDD1= 3.0V∼3.6V)
(Note 18)
BICK Period
tBCK
tBCKL
tBCKH
tLRB
tBLR
tBSS
tBSH
tSDH
tSDS
40
16
16
10
10
6
5
10
10
ns
ns
ns
ns
ns
ns
ns
ns
ns
BICK Pulse Width Low
Pulse Width High
LRCK Edge to BICK “↑”
BICK “↑” to LRCK Edge
SDTO Setup time BICK “↑”
SDTO Hold time BICK “↑”
SDTI Hold Time
(Note 21)
(Note 21)
SDTI Setup Time
TDM128 mode (TDM0 bit = “1”, TDM1 bit = “1”)
(TVDD1= 3.0V∼3.6V)
(Note 19)
BICK Period
tBCK
tBCKL
tBCKH
tLRB
tBLR
tBSS
tBSH
tSDH
tSDS
40
16
16
10
10
6
5
10
10
ns
ns
ns
ns
ns
ns
ns
ns
ns
BICK Pulse Width Low
Pulse Width High
LRCK Edge to BICK “↑”
BICK “↑” to LRCK Edge
SDTO Setup time BICK “↑”
SDTO Hold time BICK “↑”
SDTI Hold Time
(Note 21)
(Note 21)
SDTI Setup Time
MS1025-E-00
2008/10
- 17 -
AKM [ ASAHI KASEI MICROSYSTEMS ]
