ASAHI KASEI
[AK4571]
ディジタル DC特性
Ta=0 - 70°C; VD=3.0 - 3.6V; DGND=0V Measurement under static state
All digital pins except DP, DN. Schmitt hysteresis level of RSTN pin and levels of all test pins will not be tested.
Parameter
Symbol
VIH
VIL
VIHR
VILR
VIHR
VILR
VOH
Min
70%VD
Typ
Max
Units
EPDI,EPEN, EPSEL, pin “H” level input voltage
EPDI, EPEN, EPSEL pin “L” level input voltage
RSTN pin “H” level voltage
V
V
V
V
V
V
V
30%VD
0.8
2.4
2.4
2.4
RSTN pin “L” level voltage
IMUTE, OMUTE, INC, DEC pin “H” level voltage
IMUTE, OMUTE, INC, DEC pin “L” level voltage
SUSN, EPSW, STBY, EMSW, MSTAT pin
0.8
“H” level output voltage IOH= 2mA
SUSN, EPSW, STBY, EMSW, MSTAT pin
“L” level output voltage
CS, SK, EPAO pin “H” level output voltage
VOL
VOH
VOL
0.6
0.6
V
V
V
IOL= -2mA
IOH= 2mA
IOL= -2mA
2.4
2.0
CS, SK, EPAO pin “L” level output voltage
DP, DN Single Ended Receiver Threshold for “H” level
DP, DN Single Ended Receiver Threshold for pin “L” level
Input Leakage Current
VIHR
VILR
Iin
V
V
0.8
±10
mA
Rpd
100
Pull down Resistance (only EPDI pin)@3.3V Ta=25°C
kW
スイッチング特性
Ta=25°C, VA=VD=3.3V
Parameter
Master Clock Frequency
Reset input width @RSTN pin(low active)
Symbol
MCLK
Wrst
Min
-
1.0
Typ
12.000
Max
-
Units
MHz
us
Time Width for USB Reset Signal Recognition
DP<VseL & DN< VseL to USB Reset mode
Device Ready Time from USB Reset
After releasing from USB Reset to Device Ready
(Transaction can start)
ms
Trst_rec
3.0
Tdrr
10
ms
Time Width for Suspend Recognition
Tsus_rec
Tresm
4.36
ms
ms
Idle state ( DP > VseL & DN < VseL )
to Suspend mode
Resume Time from Suspend
30
First flip of D P/D N from Idle state
To Device Ready *)
Imute input width with @IMUTE pin(High active)
Omute,Dec,Inc input width with @OMUTE,DEC,INC
pin (High active)
Wimute
Wodi
10.005
2.001
ms
ms
Device Ready: VREF, X’tal oscillator and PLL are stable and standard bus transactions can proceed
MS0153-J-02
2003/3
- 9 -
AKM [ ASAHI KASEI MICROSYSTEMS ]
