ASAHI KASEI
[AK4571]
ディ タ
ジ ルDC特性
Ta=0 - 70°C; VD=3.0 - 3.6V; DGND=0V Measurement under static state
All digital pins except DP, DN. Schmitt hysteresis level of RSTN pin and levels of all test pins will not be tested.
Parameter
Symbol
Min
Typ
Max
EPDI,EPEN, EPSEL, pin “H” level input voltage
VIH
70%VD
EPDI, EPEN, EPSEL pin “L” level input voltage
VIL
30%VD
RSTN pin “H” level voltage
VIHR
2.4
RSTN pin “L” level voltage
VILR
0.8
IMUTE, OMUTE, INC, DEC pin “H” level voltage
VIHR
2.4
IMUTE, OMUTE, INC, DEC pin “L” level voltage
VILR
0.8
SUSN, EPSW, STBY, EMSW, MSTAT pin
VOH
2.4
“H” level output voltage IOH= 2mA
SUSN, EPSW, STBY, EMSW, MSTAT pin
VOL
0.6
“L” level output voltage
IOL= -2mA
CS, SK, EPAO pin “H” level output voltage
VOH
2.4
IOH= 2mA
CS, SK, EPAO pin “L” level output voltage
VOL
0.6
IOL= -2mA
DP, DN Single Ended Receiver Threshold for “H” level
VIHR
2.0
DP, DN Single Ended Receiver Threshold for pin “L” level
VILR
0.8
Input Leakage Current
Iin
±10
Rpd
100
Pull down Resistance (only EPDI pin)@3.3V Ta=25°C
Units
V
V
V
V
V
V
V
V
V
V
V
V
µA
kΩ
スイッチング特性
Ta=25°C, VA=VD=3.3V
Parameter
Symbol
Min
Typ
Master Clock Frequency
MCLK
-
12.000
Reset input width @RSTN pin(low active)
Wrst
1.0
Time Width for USB Reset Signal Recognition
Trst_rec
3.0
DP<VseL & DN< VseL to USB Reset mode
Device Ready Time from USB Reset
Tdrr
After releasing from USB Reset to Device Ready
(Transaction can start)
Time Width for Suspend Recognition
Tsus_rec
4.36
Idle state ( DP > VseL & DN < VseL )
to Suspend mode
Resume Time from Suspend
Tresm
First flip of D P/DN from Idle state
To Device Ready *)
Imute input width with @IMUTE pin(High active)
Wimute
10.005
Omute,Dec,Inc input width with @OMUTE,DEC,INC
Wodi
2.001
pin (High active)
Device Ready: VREF, X’tal oscillator and PLL are stable and standard bus transactions can proceed
Max
-
Units
MHz
us
µs
ms
10
ms
30
ms
ms
ms
MS0153-J-02
-9 -
2003/3
AKM [ ASAHI KASEI MICROSYSTEMS ]
