ASAHI KASEI
[AK4571]
Trst_rec
Tdrr
Tsus_rec
Tresm
resume time
recovery time
D+
D-
Master
Clock
Figure 1. Mode Change with respect to Bus States
トランシーバ／レシーバ特性
Ta=25°C; VD=3.3V; DGND=0V; CL=50pF
Parameter
Symbol
Pins
Conditions
Min
Typ
Max
Units
Transmitter
Data Rate
DR
DP,DN
DP, DN
11.97
12
36
12.03
MHz
DP, DN=”H”
at Iout = -10mA
DP, DN=”L”
at Iout = 10mA
at Iout=-200uA
at Iout=2.2mA
Output Impedance (Hi)
Roh
W
Output Impedance (Lo)
Rol
DP, DP
36
W
“H” level Output Voltage
“L” level Output Voltage
Tri-state Leakage Current
Rise/Fall Time
Rise/Fall Time Matching
Crossover Point
Vohd
Vold
Iolk
Trf/Tff
Trfm
Vcrs
DP, DN
DP, DN
DP, DN
DP, DN
DP, DN
DP, DN
2.8
V
V
0.3
10
20
0 < DP, DN< 3.3V
-10
4
mA
ns
%
10
100
1.65
V
Receiver
Input Common Mode range
Differential Input Level
CMR
Vdiff
DP, DN
DP, DN
0.8
0.2
2.5
V
V
| DP – DN |
MS0153-J-02
2003/3
- 10 -
AKM [ ASAHI KASEI MICROSYSTEMS ]
