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AK4550 参数 Datasheet PDF下载

AK4550图片预览
型号: AK4550
PDF下载: 下载PDF文件 查看货源
内容描述: 低功率小型16BIT CODEC [LOW POWER & SMALL PACKAGE 16BIT CODEC]
分类和应用:
文件页数/大小: 15 页 / 104 K
品牌: AKM [ ASAHI KASEI MICROSYSTEMS ]
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ASAHI KASEI  
[AK4550]  
n Power-down & Reset  
The ADC and DAC of AK4550 are placed in the power-down mode by bringing each power down pin, PWAD , PWDA  
= “L” independently and each digital filter is also reset at the same time. These resets should always be done after  
power-up. In case of the ADC, an anlog initialization cycle starts after exiting the power-down mode. Therefore, the  
output data, SDTO becomes available after 2081 cycles of LRCK clock. This initialization cycle does not affect the DAC  
operation. Figure 2 shows the power-up sequence when the ADC is powered up before the DAC power-up.  
PWAD  
2081/fs  
ADC Internal  
State  
Normal Operation  
Power-down  
Init Cycle  
Normal Operation  
PWDA  
DAC Internal  
State  
Normal Operation  
GD  
Normal Operation  
Power-down  
GD  
ADC In  
(Analog)  
ADC Out  
(Digital)  
Idle Noise  
Idle Noise  
“0”data  
DAC In  
(Digital)  
“0”data  
GD  
GD  
DAC Out  
(Analog)  
Clock In  
MCLK,LRCK,SCLK  
The clocks may be stopped.  
Mute ON  
External  
Mute  
Figure 2. Power-up Sequence  
M0068-E-01  
2000/4  
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