ASAHI KASEI
[AK4550]
n Layout Pattern Example
AK4550 requires careful attention to power supply and grounding arrangements to optimize performance.
(Please refer to AKD4550 Evaluation Board layout pattern.)
1. VDD pin should be supplied from analog power supply on system, and VSS pin should be connected to analog
ground on system. The AK4550 is placed on the analog ground plane, and near the analog ground and digital
ground split. And analog and digital ground planes should be only connected at one point. The connection point
should be near to the AK4550.
2. VDD pin should be distributed from the point with low impedance of regulator etc.
3. The series resistors are prevent on the clock lines to reduce overshoot and undershoot. To avoid digital noise
coupling to analog circuit in the AK4550, a 10pF ceramic capacitor on MCLK pin is connected with digital ground.
4. 0.1uF ceramic capacitors of VDD-VSS pins and VCOM-VSS pins should be located as close to the AK4550 as
possible. And these lines should be the shortest connection to pins.
+
4.7u
0.1u
470
+
+
Rch In
Lch In
2.2n
470
AOUTR
AOUTL
VCOM
AINR
AINL
1
2
3
4
5
6
7
8
16
15
2.2n
PWDA 14
AK4550
Analog Supply
2.3 3.6V
Reset &Power-down
Controller
VSS
PWAD
SCLK
MCLK
LRCK
SDTI
13
11
10
9
51
+
Top View
VDD
10u 0.1u
51
10P
51
DEM0
DEM1
SDTO
Analog Ground
Digital Ground
51
51
Mode Control
Figure 4. Layout Pattern Example
M0068-E-01
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AKM [ ASAHI KASEI MICROSYSTEMS ]
