ASAHI KASEI
[AK4550]
SWITCHING CHARACTERISTICS
(Ta=25°C; VDD=2.3
∼
3.6V; C
L
=20pF)
Parameter
Master Clock Timing
256fs:
Pulse Width Low
Pulse Width High
384fs:
Pulse Width Low
Pulse Width High
512fs:
Pulse Width Low
Pulse Width High
LRCK Frequency
Duty Cycle
Serial Interface Timing
SCLK Period
SCLK Pulse Width Low
Pulse Width High
LRCK Edge to SCLK “↑”
(Note 9)
SCLK “↑” to LRCK Edge
(Note 9)
LRCK Edge to SDTO (MSB)
SCLK “↓” to SDTO
SDTI Hold Time
SDTI Setup Time
Reset Timing
PWAD or PWDA Pulse Width
(Note 10)
PWAD ”↑” to SDTO Valid
Symbol
fCLK
tCLKL
tCLKH
fCLK
tCLKL
tCLKH
fCLK
tCLKL
tCLKH
fs
min
2.048
28
28
3.072
23
23
4.096
16
16
8
45
312.5
130
130
50
50
80
80
50
50
150
2081
typ
11.2896
max
12.8
Units
MHz
ns
ns
MHz
ns
ns
MHz
ns
ns
kHz
%
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1/fs
16.9344
19.2
22.5792
25.6
44.1
50
55
tSCK
tSCKL
tSCKH
tLRS
tSLR
tDLR
tDSS
tSDH
tSDS
tPW
tPWV
Notes: 9. SCLK rising edge must not occur at the same time as LRCK edge.
10. These cycles are the number of LRCK rising from PWAD rising.
M0068-E-01
-6-
2000/4
AKM [ ASAHI KASEI MICROSYSTEMS ]
