ASAHI KASEI
[AK4550]
SYSTEM DESIGN
Figure 3 shows the system connection diagram. An evaluation board[AKD4550] is available which demonstrates
application circuit, optimum layout, power supply arrangements and measurement results.
+
4.7u
0.1u
470
Rch In
Lch In
+
+
2.2n
470
1
2
3
4
5
6
7
8
VCOM
AINR
AINL
AOUTR 16
AOUTL 15
Reset
Reset
2.2n
10u
14
13
PWDA
PWAD
AK4550
Analog Supply
2.3 3.6V
VSS
0.1u
+
Top View
VDD
SCLK 12
MCLK 11
LRCK 10
DEM0
DEM1
SDTO
Controller
SDTI
9
Analog Ground
System Ground
Mode
Control
Figure 3. System Connection Diagram Example
Notes:
- LRCK=fs, 32fs ≤ SCLK ≤ 96fs, MCLK=256fs/384fs/512fs.
- When AOUT drives some capacitive load, some resistor should be added in series between AOUT and capacitive
load.
- Electrolytic capacitor value of VCOM depends on low frequency noise of supply voltage.
M0068-E-01
2000/4
- 11 -
AKM [ ASAHI KASEI MICROSYSTEMS ]
