ASAHI KASEI
[AK4527B]
LRCK
fs
32.0kHz
44.1kHz
48.0kHz
88.2kHz
96.0kHz
MCLK (MHz)
Sampling
Speed
256fs
512fs
16.3840
22.5792
24.5760
-
-
-
-
Normal
Double
22.5792
24.5760
-
Table 5. System Clock Example (Auto Setting Mode)
n De-emphasis Filter
The AK4527B includes the digital de-emphasis filter (tc=50/15µs) by IIR filter. This filter corresponds to three sampling
frequencies (32kHz, 44.1kHz, 48kHz). De-emphasis of each DAC can be set individually by register data of DEMA1-C0
(DAC1: DEMA1-0, DAC2: DEMB1-0, DAC3: DEMC1-0, see “Register Definitions”).
Mode
Sampling Speed
Normal Speed
Normal Speed
Normal Speed
Normal Speed
Double Speed
Double Speed
Double Speed
Double Speed
DEM1
DEM0
DEM
44.1kHz
OFF
48kHz
32kHz
OFF
OFF
OFF
OFF
0
1
2
3
4
5
6
7
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Default
Table 6. De-emphasis control
n Digital High Pass Filter
The ADC has a digital high pass filter for DC offset cancel. The cut-off frequency of the HPF is 0.9Hz at fs=44.1kHz and
also scales with sampling rate (fs).
n Audio Serial Interface Format
Four serial data modes can be selected by the DIF0 and DIF1 pins (P/S = “H”) or bits (P/S = “L”) as shown in Table 7. In
all modes the serial data is MSB-first, 2’s compliment format. The SDTO is clocked out on the falling edge of BICK and
the SDTI/DAUX are latched on the rising edge of BICK.
Figures 1 4 shows the timing at SDOS = “L”. In this case, the SDTO outputs the ADC output data. When SDOS = “H”,
the data input to DAUX is converted to SDTO’s format and output from SDTO. Mode 2 and mode 3 in SDTI/DAUX
input formats can be used for 16-20bit data by zeroing the unused LSBs.
Mode DIF1 DIF0
SDTO
SDTI1-3, DAUX
20bit, LSB justified
24bit, LSB justified
24bit, MSB justified
24bit, IIS (I2S)
LRCK
H/L
H/L
H/L
L/H
0
1
2
3
0
0
1
1
0
1
0
1
24bit, MSB justified
24bit, MSB justified
24bit, MSB justified
24bit, IIS (I2S)
Default
Table 7. Audio data formats
MS0056-E-00
2000/10
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AKM [ ASAHI KASEI MICROSYSTEMS ]
