ASAHI KASEI
[AK4387]
LRCK
fs
MCLK
BICK
64fs
128fs
192fs
176.4kHz 22.5792MHz 33.8688MHz 11.2896MHz
192.0kHz 24.5760MHz 36.8640MHz 12.2880MHz
Table 4. System Clock Example (Quad Speed Mode @Manual Setting Mode)
MCLK
1152fs
Sampling Speed
Normal (fs 32kHz)
≤
512fs
256fs
128fs
768fs
384fs
192fs
Normal
Double
Quad
Table 5. Sampling Speed (Auto Setting Mode: Default)
LRCK
fs
MCLK (MHz)
Sampling
Speed
128fs
192fs
256fs
384fs
512fs
768fs
1152fs
32.0kHz
44.1kHz
48.0kHz
88.2kHz
96.0kHz
176.4kHz
192.0kHz
-
-
-
-
-
-
-
-
-
-
-
-
-
-
16.3840
22.5792
24.5760
24.5760 36.8640
Normal
33.8688
-
-
-
-
-
-
36.8640
22.5792
24.5760
33.8688
36.8640
-
-
-
-
-
-
-
-
Double
Quad
-
-
22.5792
24.5760
33.8688
36.8640
-
-
-
-
Table 6. System Clock Example (Auto Setting Mode)
Audio Serial Interface Format
Data is shifted in via the SDTI pin using BICK and LRCK inputs. The DIF0-2 as shown in Table 7 can select five serial
data modes. In all modes the serial data is MSB-first, 2’s compliment format and is latched on the rising edge of BICK.
Mode 2 can be used for 16/20 MSB justified formats by zeroing the unused LSBs.
Mode DIF2 DIF1 DIF0 SDTI Format
BICK
Figure
Figure 1
Figure 2
Figure 3
0
1
2
0
0
0
0
0
1
0
1
0
16bit LSB Justified
20bit LSB Justified
24bit MSB Justified
24bit I2S Compatible
32fs
40fs
48fs
≥
≥
≥
Default
3
4
0
1
1
0
1
0
Figure 4
Figure 2
48fs
48fs
≥
≥
24bit LSB Justified
Table 7. Audio Data Formats
MS0429-E-00
2005/09
- 9 -
AKM [ ASAHI KASEI MICROSYSTEMS ]
