欢迎访问ic37.com |
会员登录 免费注册
发布采购

AK4387ET 参数 Datasheet PDF下载

AK4387ET图片预览
型号: AK4387ET
PDF下载: 下载PDF文件 查看货源
内容描述: 106分贝192kHz的24位双声道ツヒDAC [106dB 192kHz 24-Bit 2ch ツヒ DAC]
分类和应用: 转换器数模转换器光电二极管
文件页数/大小: 21 页 / 246 K
品牌: AKM [ ASAHI KASEI MICROSYSTEMS ]
 浏览型号AK4387ET的Datasheet PDF文件第4页浏览型号AK4387ET的Datasheet PDF文件第5页浏览型号AK4387ET的Datasheet PDF文件第6页浏览型号AK4387ET的Datasheet PDF文件第7页浏览型号AK4387ET的Datasheet PDF文件第9页浏览型号AK4387ET的Datasheet PDF文件第10页浏览型号AK4387ET的Datasheet PDF文件第11页浏览型号AK4387ET的Datasheet PDF文件第12页  
ASAHI KASEI  
[AK4387]  
OPERATION OVERVIEW  
„ System Clock  
The external clocks, which are required to operate the AK4387, are MCLK, LRCK and BICK. The master clock (MCLK)  
should be synchronized with LRCK but the phase is not critical. The MCLK is used to operate the digital interpolation  
filter and the delta-sigma modulator. There are two methods to set MCLK frequency. In Manual Setting Mode (ACKS bit  
= “0”: Register 00H), the sampling speed is set by DFS0/1(Table 1). The frequency of MCLK at each sampling speed is  
set automatically. (Table 2~4). After exiting reset (RSTN pin = “ ”), the AK4387 is in Auto Setting Mode. In Auto  
Setting Mode (ACKS bit = “1”: Default), as MCLK frequencyis detected automatically (Table 5), and the internal master  
clock becomes the appropriate frequency (Table 6), it is not necessary to set DFS0/1.  
All external clocks (MCLK, BICK and LRCK) should always be present whenever the AK4387 is in the normal operation  
mode (RSTN pin = ”H”). If these clocks are not provided, the AK4387 may draw excess current and may fall into  
unpredictable operation. This is because the device utilizes dynamic refreshed logic internally. The AK4387 should be  
reset by RSTN pin = “L” after threse clocks are provided. If the external clocks are not present, the AK4387 should be in  
the power-down mode (RSTN pin = “L”). After exiting reset at power-up etc., the AK4387 is in the power-down mode  
until MCLK and LRCK are input.  
DFS1  
DFS0  
Sampling Rate (fs)  
Default  
0
0
1
0
1
0
Normal Speed Mode  
8kHz~48kHz  
60kHz~96kHz  
120kHz~192kHz  
Double Speed Mode  
Quad Speed Mode  
Table 1. Sampling Speed (Manual Setting Mode)  
LRCK  
fs  
MCLK  
512fs  
BICK  
64fs  
8.1920MHz 12.2880MHz 16.3840MHz 24.5760MHz 36.8640MHz 2.0480MHz  
256fs  
384fs  
768fs  
1152fs  
32.0kHz  
44.1kHz 11.2896MHz 16.9344MHz 22.5792MHz 33.8688MHz  
48.0kHz 12.2880MHz 18.4320MHz 24.5760MHz 36.8640MHz  
N/A  
N/A  
2.8224MHz  
3.0720MHz  
Table 2. System Clock Example (Normal Speed Mode @Manual Setting Mode)  
LRCK  
fs  
MCLK  
BICK  
64fs  
128fs  
192fs  
256fs  
384fs  
88.2kHz 11.2896MHz 16.9344MHz 22.5792MHz 33.8688MHz 5.6448MHz  
96.0kHz 12.2880MHz 18.4320MHz 24.5760MHz 36.8640MHz 6.1440MHz  
Table 3. System Clock Example (Double Speed Mode @Manual Setting Mode)  
MS0429-E-00  
2005/09  
- 8 -  
 复制成功!