[AK4127]
• Input PORT: Slave Mode, IBICK lock mode (64fsi), 24bit MSB justified
• Output PORT: Master mode, 24bit MSB justified
• Dither = OFF
470
10μ
1.0n
Supply
3.0 ~ 3.6V
1
2
3
4
5
6
7
8
9
FILT
AVDD 30
DVSS 29
0.1μ
0.1μ
0.22μ
AVSS
PDN
Reset
DVDD 28
128fso
fso
SMUTE
DITHER
PLL2
OMCLK 27
OLRCK 26
OBICK 25
SDTO 24
DSP
64fso
fsi
ILRCK
IBICK
SDTI
AK4127
64fsi
ODIF1 23
ODIF0 22
CMODE2 21
CMODE1 20
CMODE0 19
IMCLK 18
OBIT1 17
OBIT0 16
DSP, uP
10 IDIF0
11 IDIF1
12 IDIF2
13 PLL0
14 PLL1
15 UNLOCK
Note:
- AVSS and DVSS of the AK4127 must be distributed separately from the ground of external digital
devices (MPU, DSP etc.).
- All digital input pins must not be left floating.
Figure 20. Typical Connection Diagram (Master mode)
1. Grounding and Power Supply Decoupling
The AK4127 requires careful attention to power supply and grounding arrangements. Alternatively if AVDD and DVDD
are supplied separately, the power up sequence is not important. Decoupling capacitors should be as near to the AK4127 as
possible, with the small value ceramic capacitor being the nearest.
MS0593-E-01
2007/07
- 24 -
AKM [ ASAHI KASEI MICROSYSTEMS ]
