[AK4127]
■ Dither
The AK4127 has a dither circuit. The dither circuit adds the dither to the LSB of the output data, which is the value of the
OBIT1-0 pins, by DITHER pin = “H” regardless of the SRC mode or the SRC bypass mode.
■ System Reset
Bringing the PDN pin = “L” sets the AK4127 power-down mode and initializes the digital filter. The AK4127 should be
reset once by bringing the PDN pin = “L” when power-up. When the PDN pin = “L”, the SDTO output is “L”. The SDTO
valid time is 100ms. Until the output data becomes valid, the SDTO pin outputs “L”.
Case 1
External clocks
(Input port)
Input Clocks 1
Input Data 1
Input Clocks 2
Input Data 2
Don’t care
Don’t care
Don’t care
Don’t care
Don’t care
Don’t care
SDTI
External clocks
(Output port)
Output Clocks 1
Output Clocks 2
PDN
< 100ms
< 100ms
Normal
operation
Normal
operation
PLL lock &
fs detection
PLL lock &
fs detection
PD
Power-down
Power-down
“0” data
(Internal state)
SDTO
“0” data
Normal data
“0” data
Normal data
UNLOCK
Figure 15. System Reset
Case 2
External clocks
(Input port)
Input Clocks
Don’t care
Don’t care
Don’t care
(No Clock)
SDTI
Input Data
(Don’t care)
(Don’t care)
External clocks
(Output port)
Output Clocks
PDN
< 100ms
PLL lock &
fs detection
Normal
operation
Power-down
PLL Unlock
Power-down
“0” data
(Internal state)
SDTO
“0” data
Normal data
UNLOCK
Figure 16. System Reset 2
MS0593-E-01
2007/07
- 20 -
AKM [ ASAHI KASEI MICROSYSTEMS ]
