[AK4127]
■ PLL Loop Filter
The C1 and R should be connected in series and attached between the FILT pin and AVSS in parallel with C2. Please be
careful the noise onto the FILT pin. When using IBICK, the value of external element is not dependent on the IBICK
input frequency.
AK4127
FILT
R
C2
C1
AVSS
Figure 18. PLL Loop Filter
[Input PORT in slave mode]
1. When using ILRCK
PLL2
L
PLL1
L
PLL0
L
ILRCK
C2 [nF]
R [Ω]
1.8k ± 5%
1k ± 5%
1.5k ± 5%
1k ± 5%
1.5k ± 5%
1k ± 5%
C1 [μF]
8k ∼ 96kHz
0.68 ± 30%
1.0 ± 30%
0.68 ± 30%
1.0 ± 30%
0.68 ± 30%
1.0 ± 30%
0.68 ± 30%
0.68 ± 30%
2.2 ± 30%
0.68 ± 30%
2.2 ± 30%
0.68 ± 30%
2.2 ± 30%
0.68 ± 30%
8k ∼ 216kHz
16k ∼ 216kHz
8k ∼ 216kHz
16k ∼ 216kHz
8k ∼ 216kHz
16k ∼ 216kHz
L
L
L
L
H
H
H
L
H
1.5k ± 5%
Table 6. PLL Loop Filter (ILRCK Mode)
- Note. Smaller value can be selected for the capacitors (C1, C2) in case of ILRCK range from 16kHz to 216kHz..
2. When using IBICK
PLL2
H
PLL1
*
PLL0
*
ILRCK
C2 [nF]
R [Ω]
470 ± 5%
C1 [μF]
0.22 ± 30%
8k ∼ 216kHz
1.0 ± 30%
Table 7. PLL Loop Filter (IBICK Mode, *: Don’t care)
Note. The IBCIK must be continuous except when the clocks are changed.
Note. IBCIK = 32fsi is supported only 16bit LSB justified and I2S Compatible.
[Input PORT in master mode]
1. When IMCLK is 256fs, 384fs, 512fs or 768fs, any external parts shown in Figure 18 are not required.
2. When IMCLK is 128fs or 192fs, the external parts shown in Table 7 are required.
MS0593-E-01
2007/07
- 22 -
AKM [ ASAHI KASEI MICROSYSTEMS ]
