[AK4127]
■ Internal Reset Function for Clock Change
The AK4127 is reset automatically when the output clock is stopped. If the output clock is started again, normal data is
output within 100ms.
■ Sequence of Changing Clocks
The change sequence of the clock supplied to AK4127 is shown in Figure 17.
External clocks
(Input port
Clocks 1
Clocks 2
Don’t care
or Output port)
PDN pin
< 100ms
PLL lock &
fs detection
(Internal state) Normal operation Power-down
Note1
Normal operation
Normal data
SDTO
Normal data
SMUTE (Note2,
recommended)
1024/fso
1024/fso
0dB
Att.Level
∞
- dB
Figure 17. Sequence of changing clocks
Note 1. The data on SDTO may cause a clicking noise. To prevent this, set “0” to the SDTI from GD before the PDN
pin changes to “L”. It makes the data on SDTO remain as “0”.
Note 2. SMUTE can also be used to remove the unknown data.
■ UNLOCK pin
The UNLOCK pin outputs “L” when the internal PLL is locked. When the internal PLL is unlocked, the UNLOCK pin
outputs “H” and the SDTO = “0”. When the PDN pin = “L”, the UNLOCK pin outputs “H”.
MS0593-E-01
2007/07
- 21 -
AKM [ ASAHI KASEI MICROSYSTEMS ]
