ASAHI KASEI
[AK4115]
Error Handing for ELRCK (PSEL = “1”)
The followings two events cause the INT0 and INT1 pins to show the status of the interrupt conditions. When the PLL is
OFF (Clock Operation Mode 1), the INT0 and INT1 pins go to “L”.
1. UNLCK : PLL unlock state detect
“1” when the PLL loses lock.
The AK4115 loses lock when the phase difference between the current ELRCK and the previous
ELRCK is more than 5% after “4 x fs”.
The PLL is locked when the phase difference between the current ELRCK and the pervious
ELRCK is less than 2% after “256 x fs”.
When the PLL loses lock, the PLL goes to a free running state. The sampling frequency is
typically 11kHz in this case.
2. FS3-0
: Sampling frequency detection
FS3-0 bits are updated every “128 x fs”. When FS3-0 bits are changed, the STC bit is not changed
and the INT0 and INT1 pins go to “H” after “1 x fs”
In this mode, INT0 does not have the hold function. Therefore, INT0 and INT1 go to “L” at the same time when those
events are removed. Each INT0/1 pins can mask those two events individually.
1. Parallel Mode
In parallel mode, INT0 triggers UNLCK, and INT1 triggers when FS3-0 bits are changed. INT0 and INT1 go “L” after
each event is removed.
2. Serial Mode
In serial mode, INT1 and INT0 outputs an ORed signal based on the two interrupt events shown above. When masked,
the interrupt event does not affect operation of the INT1-0.
Event
Pin
UNLCK
Change of FS3-0 bits
SDTO
“L”
Output
TX
Output
Output
1
0
x
1
Table 27. Error Handling (x: Don’t care)
MS0573-E-00
2006/12
- 39 -
AKM [ ASAHI KASEI MICROSYSTEMS ]
