9.4 ns
Tx
H
TCn
TDn[9:0]
Tx
CDH
Case A. Tx Half Rate SDR Timing
9.4 ns
Tx
H
Tx
H
TCn
TDn[9:0]
Tx
CDH
Tx
CDH
Case B. Tx Full Rate DDR Timing
Test Conditions: V
IH
= V
DDQ
, V
IL
= GND
Figure 9. Transmitter Timing Diagram.
Table 4. HDMP-2689 Transmitter Section Timing Characteristics,
T
C
= 0°C to T
C
= 85°C, V
DDQ
= 2.3 to 2.7 V, V
DD
= 1.7 to 1.9 V, V
DDA
= 1.7 to 1.9 V
Symbol
1G
Tx
CDS[1,2]
Tx
H [2]
t_TXlat_buffer
[3]
t_TXlat_codec
[3]
2G
Tx
CDS [1,2]
Tx
H [2]
t_TXlat_buffer
[3]
t_TXlat_codec
[3]
Parameters
Units
Min
Typ
Max
Clock to data skew time; the data must be stable by T
CDS
after the clock edge to
guarantee correct clocking of the data
Hold time; the time after the clock edge until which the data must remain stable
to guarantee correct clocking of the data
Transmitter latency; the time between the latching edge of the transmit byte clock
TCn and the leading edge of the first transmitted serial output bit in buffer mode
Transmitter latency; the time between the leading edge of the transmit byte clock
TCn and the leading edge of the first transmitted serial output bit in codec mode
ps
ps
ns
bits
ns
bits
2000
80
85
90
95.5
300
Clock to data skew time; the data must be stable by T
CDS
after the clock edge to
guarantee correct clocking of the data
Hold time; the time after the clock edge until which the data must remain stable to
guarantee correct clocking of the data
Transmitter latency; the time between the latching edge of the transmit byte clock
TCn and the leading edge of the first transmitted serial output bit in buffer mode
Transmitter latency; the time between the leading edge of the transmit byte clock
TCn and the leading edge of the first transmitted serial output bit in codec mode
ps
ps
ns
bits
ns
bits
2000
65
138
70
149
300
Notes:
1. This clock-to-data skew time is equivalent to –300ps setup time.
2. Measurement conditions were V
IH
= V
DDQ
, V
IL
= GND.
3. Due to the FIFO which aligns the phase of the internal chip clock with the transmit byte clock (TCn) and the asynchronous nature of the chip reset, the
typical latency varies; a maximum of the typical range is given.
9
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