10-BIT CHAR B
10-BIT CHAR C
RXP/N
RD[0]
RXLAT
RD[0:9]
RC
10-BIT CHAR A
10-BIT CHAR B
RD[9]
Figure 14. Receiver Latency.
Table 7. IEEE JTAG 1149.1 Instructions.
Instruction
EXTEST
SAMPLE
CLAMP
HIGHZ
BYPASS
Opcode
00000_00000
00000_00010
00000_00100
00000_01000
11111_11111
Description
Causes boundary JTAG registers to capture their inputs, shift, and output to pads.
Causes boundary JTAG registers to capture their inputs.
Causes boundary JTAG registers to output their values to pads.
Causes pads to be tri-stated.
Connects the bypass register between TDI and TDO.
Table 8. Format of a Management Frame.
Pr
Read
Write
11...1
11...1
St
01
01
Op
10
01
PhyAdd
aaaaa
aaaaa
RegAdd
rrrrr
rrrrr
TA
Z0
10
Data
DDDDDDDDDDDDDDDD
DDDDDDDDDDDDDDDD
IDLE
Z
Z
MDC
MDIO
Figure 15. MDIO and MDC Timing.
Table 9. MDIO Timing Characteristics,
T
C
= 0°C to T
C
= 85°C, V
DDQ
= 2.3 to 2.7 V, V
DD
= 1.7 to 1.9 V, V
DDA
= 1.7 to 1.9 V
Symbol
Driving
T
DELAY
T
MDC
Receiving
T
SU
T
H
Parameters
Units
Min
Typ
Max
MDC rising edge to MDIO data true or MDIO released
MDC frequency
ns
MHz
0
300
2.5
Set up time: MDIO to MDC rising edge
Hold time: MDC rising edge to MDIO changing
ns
ns
10
10
Note: For more information, see the IEEE 802.3 part 3 22.3.4, “MDIO timing relationship to MDC.”
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