HDMP-2689 Receiver Section Timing Characteristics,
T
C
= 0°C to T
C
= 85°C, V
DDQ
= 2.3 to 2.7 V, V
DD
= 1.7 to 1.9 V, V
DDA
= 1.7 to 1.9 V
Symbol
PWreset
f lockRX
B_sync_lock
B_sync_rate
1G
RX
S[1]
RX
H [1]
t_RXlat_buffer
Parameters
Width of reset pulse
The time that the RX PLL takes to frequency lock to the data after reset
Bit Sync time after f lockRX
Bit Sync time after rate switch
Units
ns
µs
bits
µs
Min
100
Typ
Max
500
2500
100
Setup time: the time before the clock edge that the data will be stable
Hold time; the time after the clock edge until which the data will remain stable
Receiver latency; the timing between the leading edge of the first received serial
bit of a parallel data word and the leading edge of the corresponding parallel output
word in buffer mode
Receiver latency; the timing between the leading edge of the first received serial
bit of a parallel data word and the leading edge of the corresponding parallel output
word in codec mode
ps
ps
ns
bits
ns
bits
2700
1500
50
53
60
64
t_RXlat_codec
2G
RX
S [1]
RX
H [1]
t_RXlat_buffer
Setup time: the time before the clock edge that the data will be stable
Hold time; the time after the clock edge until which the data will remain stable
Receiver latency; the timing between the leading edge of the first received serial
bit of a parallel data word and the leading edge of the corresponding parallel output
word in buffer mode
Receiver latency; the timing between the leading edge of the first received serial
bit of a parallel data word and the leading edge of the corresponding parallel output
word in codec mode
ps
ps
ns
bits
ns
bits
1200
1400
30
64
35
75
t_RXlat_codec
Notes:
1. Tested under load conditions described in Figure 12, with V
IH
= V
REF
+ 0.18 and V
IL
= V
REF
– 0.18.
VTERM (VDDQ/2)
50
Ω
Z
0
= 50
Ω
DELAY = 1.0 - 2.0ns
SSTL_2
OUTPUT DRIVER
Note:
Register 23 set to 0x1218.
C
LOAD
= 4 pF
Figure 12. SSTL_2 Output Test Conditions.
power supplies and RFCN/
RFCP have stabilized
program MDIO
500
µs
f
lockRX
100 ns
PW reset
RSTN
20
µs
Figure 13. Externally Applied Reset (not to scale).
11
AGILENT [ AGILENT TECHNOLOGIES, LTD. ]
