Receiver Description
The HDMP-2689 receiver con-
tains four independent channels,
each with its own input amplifier
with equalization, clock recovery
PLL, deserializer, comma detec-
tion and byte clock generation.
Depending on the PMX mode, the
data may also pass through an
8B/10B decoder.
High Speed Input
In normal operation, serial data
is accepted at RXnP/N and
converted into parallel data to
drive RDn[9:0]. See Figure 5 for
the input configuration. In
parallel loopback mode, the
internal serial output signal from
the transmitter section is used to
generate RDn[9:0]. Loopback is
discussed in more detail in the
section on Test.
Receiver Loss of Signal
When the peak-to-peak differen-
tial amplitude at the RXnP/N
input is too small, LOSn is set to
logic 1. When the signal at RXnP/
N is a valid amplitude, LOSn is
set to logic 0.
If RXnP/N
≥
300 mV peak-to-
peak differential,
LOSn = logic 0
If 150 mV < RXnP/N < 300 mV
peak-to-peak differential,
LOSn is undefined
If RXnP/N
≤
150 mV peak-to-
peak differential,
LOSn = logic 1
Optionally, through MII register
17, LOSn can also be forced to
logic 1 if the receiver PLL is not
locked.
RX PLL/Clock Recovery
The receiver frequency and
phase locks onto the incoming
serial data stream and recovers
the bit clock. The RX PLL locks
onto the input data by frequency
locking onto the 106.25 MHz
LVPECL reference clock and then
5
phase locking onto the selected
input data stream. The received
clock locks to the incoming data
or free runs at the selected
frequency in the absence of
incoming data. An internal signal
detection circuit monitors the
presence of the input and in-
vokes phase detection as the data
stream appears. Once bit locked,
the receiver generates the high-
speed sampling clock used to
deserialize the data.
Byte Sync and Comma Detect
As the 10-bit parallel data is
recovered from the high-speed
serial bit stream, the first seven
bits of the K28.5+ positive
disparity comma character
(0011111xxx) and of the K28.5-
negative disparity comma charac-
ter (1100000xxx) are detected.
The proper parallel data edge is
selected out of the bit stream so
that the next comma character
starts at RDn[9] in buffer mode.
When a comma character is
detected and realignment of the
receive byte clock is necessary,
the clocks are stretched (never
slivered) to the next correct
alignment position. The recov-
ered clock will be aligned by the
start of the next four-byte
ordered set after K28.5+ or
K28.5- is detected. By default, in
buffer mode, the start of the next
ordered set will be aligned with
the falling edge of RCn. In codec
mode (PMX=1), by default the
RCn clock is not realigned, and
the comma may appear at either
edge. The default alignments may
be changed by programming MII
register 17. Unless comma edge
alignment is disabled in MII
register 17, comma characters
must not be transmitted in
consecutive bytes so that the
receive byte clocks may maintain
their proper recovered frequen-
cies. Furthermore, RX byte align
should be disabled (using MII
register 24) if PRBS data is being
received.
SSTL_2 Outputs
As discussed for the transmitter
parallel inputs, the bit ordering is
different for buffer and codec
modes. See Figure 4 and earlier
Data Input section for additional
details.
The HDMP-2689 presents the
10-bit parallel recovered data
(RDn[9:0]), properly aligned to
the receive byte clock (RCn) as
shown in Figure 11 and Table 5,
as single-ended SSTL_2 compli-
ant signals. The HDMP-2689
expects SSTL_2 compatible
signals at the TDn[9:0] and TCn
pins. See Figure 7 for a simplified
schematic of the input and
output drivers, and Figure 8 for
the recommended termination
configuration. For proper opera-
tion of the terminated SSTL_2
drivers, register 23 must be
configured as described in
Management Interface Registers,
page
27.
(Set register 23 to
0x1218). For best results use a
low inductance VTERM plane to
terminate the 50
Ω
resistors
close to the HDMP-2689 TX
inputs. In addition, decouple the
VTERM plane with 0.1
µF
local to
each 10-bit channel to reduce
simultaneously switching output
(SSO) noise on the inputs. The
HDMP-2689 works with MAC
devices whose VDDQ voltage is
nominally 2.5 V. In addition, the
HDMP-2689 provides a VREF
output pin which may be used at
the protocol IC in order to
differentially detect a high or a
low on RDn[9:0]. Alternatively,
this voltage may be generated on
the PCB using a resistor divider
from VDDQ while ignoring the
VREF output of the HDMP-2689.
AGILENT [ AGILENT TECHNOLOGIES, LTD. ]
