Reference Clock Input
The HDMP-2689 accepts a
differential LVPECL reference
clock input at 106.25 MHz (see
Figure 3 for configuration). This
reference clock is used by the TX
PLL to acquire frequency lock
and generate the base frequency
of operation.
0.1µF
RFCP
100Ω
RFCN
0.1µF
Figure 3. Reference Clock Input Configuration.
Data Input
The transmitter is designed to
accept either of two formats of
parallel input data:
• 9-bit data consisting of an
8-bit word plus a 1-bit K
character flag (Z), encoded on
chip with 8B/10B
• 10-bit data already encoded in
a DC-balanced code (over a
minimum length of 20 bits)
such as 8B/10B
The PMX pin is set to select the
data format. Depending on the
format, the data may undergo
encoding before serialization. See
Table 1 for PMX encoding defini-
tions and data processing.
Table 2 contains a summary of
the data formats. Note that for
the buffer mode (PMX=0), bit a,
which corresponds to TDn9, is
serialized first. For example, for
K28.5 (0011111010), if the MAC’s
Out0 through Out9 bits corre-
spond to 0011111010, then the
HDMP-2689’s TDA9 through
TDA0 are connected to the MAC’s
Out0 through Out 9. The TDA9
bit is serialized first. Similarly on
the RX side, the very first bit
received is RDA9 (MSB) which is
In0 for the MAC. See Figure 4 for
MAC to HDMP-2689 connections.
(Channel A, shown in the figure,
is representative of all four
channels.)
For codec mode, the MAC’s Out0
through Out9 should be con-
nected to TDA0 through TDA9.
For example, if 1bc=01 1011 1101
is coming from the MAC for
encoding, Out0 (assuming this is
the LSB from the MAC) is 1, Out1
is 0 and so on. After encoding,
the result is a comma,
0011111010 (or 1100000101),
with the leading 00 (or 11) bits
coming first on the serial output.
The RX side behaves in a similar
fashion. The parallel input data
arrives on SSTL_2 inputs and is
captured by data latches which
are clocked by the local transmit
clocks (TC[A-D]). The TX_FIFO
Codec Mode
Out9
Out8
.
.
.
phase aligns the data with the
internal core clock.
8B/10B Encoding
The HDMP-2689 provides a global
8B/10B line coding option. The
characters defined by this code
ensure a DC balanced serial data
stream, which enables clock
recovery at the receiver. The
8B/10B code distinguishes
D-characters, used for data
transmission, from K-characters,
used for control or protocol
functions. A byte error code can
be designated as the replacement
data for an erroneous data word
by programming bits 14 through
6 of management interface
register 19.
Half Rate/Full Rate
The HDMP-2689 supports two
transmit data rates as detailed in
Table 3. The 10-bit wide parallel
data is multiplexed into a
1.0625 GBd (half rate) or
2.125 GBd (full rate) serial data
stream using internally gener-
ated high-speed clocks. The data
bits are transmitted sequentially
from TDn[9] to TDn[0] (bit
ordering for buffer and codec
modes is shown in Table 2). The
output serial data rate is selected
by programming bit 15 in man-
agement interface register 17.
Buffer Mode
Out9
Out8
.
.
.
.
.
.
.
.
.
TDA0
TDA1
.
.
.
TXA
TDA9(ERR)
TDA8(Z)
.
.
.
TXA
serial
data out
Out0
TDA9
Out0
TDA0(D0)
serial
data out
MAC
Chip
In9
In8
.
.
.
.
.
.
HDMP-
2689
RDA0
RDA1
.
.
.
MAC
Chip
In9
In8
RXA
HDMP-
2689
RDA9(ERR)
RDA8(Z)
.
.
.
.
.
.
In0
RDA9
serial
data in
.
.
.
RXA
In0
RDA0(D0)
serial
data in
Figure 4. MAC to HDMP-2689 Interconnect.
3
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