HDMP-1685A TRx I/O Definition, continued
Name
Pin
Type
Signal
SO0+
SO0-
SO1+
SO1-
SO2+
SO2-
SO3+
SO3-
R05
P05
R07
P07
P11
R11
P13
R13
HS_ OUT Serial Data Outputs: High-speed outputs. These lines are active except when
PLUP is high, in which case these outputs are held static at logic 1.
SYNC
R17
I-SSTL2
Enable Byte Sync Input: When high, turns on the internal byte sync functions to allow
clock synchronization to a comma character of positive disparity (0011111XXX). When
the line is low, the function is disabled and will not reset registers and clocks, or strobe
the SYN [0:3] lines.
SYN0
SYN1
SYN2
SYN3
F02
A04
B10
B15
O-SSTL2 Byte Sync Outputs: Active high outputs. Used to indicate detection of a comma
character of positive disparity (0011111XXX) when SYNC is enabled.
TC
K17
I-SSTL2
I-SSTL2
Transmit Byte Clock: This signal is used to latch transmit data for all channels
into the IC.
TX00
TX01
TX02
TX03
TX04
TX10
TX11
TX12
TX13
TX14
TX20
TX21
TX22
TX23
TX24
TX30
TX31
TX32
TX33
TX34
N01
N02
N03
N04
M01
J01
J02
J03
J04
H01
G16
G15
G14
H17
H16
L17
Data Inputs: Four 5-pin data busses. TX [0:3] [0] are the first bits transmitted.
L16
L15
L14
M17
VREFT
P01
D07
I-S
TX Parallel Interface SSTL_2 Reference Voltage: Voltage reference derived from
2 resistor network with V (ASIC) as supply, as recommended in Figure 11.
DDQ
VREFR
O-S
RX Parallel Interface SSTL_2 Reference Voltage: Provided by HDMP-1685A.
Drives the VREF input of the ASIC.
15
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