HDMP-1685A TRx I/O Definition
Name
Pin
Type
Signal
CAP0
P09
C
Loop Filter Capacitor: A loop filter capacitor for the internal PLLs must be connected
across the CAP0 and CAP1 pins. (typical value = 0.1 µF)
CAP1
PLUP
R09
N14
I-SSTL2
Parallel Loopback Enable Input: When set high, a high-speed serial signal from the
transmitter section’s serial output select block, reflecting TX data, is driven to the
receiver section’s serial input select block. RX data reflects this serial signal. Also
when in parallel loopback mode, the SO [0:3]+/- outputs are held static at logic 1.
RFCT
R01
I-LVTTL
LVTTL Reference Clock: RFCT is a 125 MHz clock signal supplied to the IC.
RC00
RC01
RC10
RC11
RC20
RC21
RC30
RC31
E01
E02
A05
B05
C10
D10
B16
B17
O-SSTL2 Receiver Byte Clocks: The receiver sections drive 125 MHz receive byte
clocks RC [0:3] [0:1].
RX00
RX01
RX02
RX03
RX04
RX10
RX11
RX12
RX13
RX14
RX20
RX21
RX22
RX23
RX24
RX30
RX31
RX32
RX33
RX34
D01
D02
E03
E04
C01
A06
B06
C06
D06
A07
B11
A12
B12
C12
D12
C17
D14
D15
D16
D17
O-SSTL2 Data Outputs: Four 5-pin data busses. RX [0:3] [0] are the first bits received.
SI0+
SI0-
SI1+
SI1-
SI2+
SI2-
SI3+
SI3-
U04
U03
U07
U06
U11
U10
U14
U13
HS_IN
Serial Data Inputs: High-speed inputs. Serial data are accepted from the SI [0:3]+/-
inputs except when PLUP is high.
14
AGILENT [ AGILENT TECHNOLOGIES, LTD. ]
