6
HDMP-1637A (Receiver Section)
Timing Characteristics
T
A
= 0°C to +70°C, V
CC
= 3.15 V to 3.45 V
Symbol
f_lock
b_sync
[1,2]
t
valid_before
t
valid_after
t
duty
t
A-B[4]
t_rxlat
[3]
Parameter
Frequency Lock at Powerup
Bit Sync Time
Time Data Valid Before Rising Edge of RBC
Time Data Valid After Rising Edge of RBC
RBC Duty Cycle
Rising Edge Time Difference between
RBC0 and RBC1
Receiver Latency
Units
µs
bits
nsec
nsec
%
nsec
nsec
bits
Min.
Typ.
Max.
500
2500
2.5
1.5
40
7.5
22.4
28.0
60
8.5
Notes:
1. This is the recovery time for input phase jumps, per the Fibre Channel Specification X3.230-1994 FC-PH Standard, Sec 5.3.
2. Tested using C
PLL
= 0.1
µF.
3. The receiver latency, as shown in Figure 6, is defined as the time between receiving the first serial bit of a parallel data word
(defined as the first edge of the first serial bit) and the clocking out of that parallel word (defined by the rising edge of the receive
byte clock, either RBC1 or RBC0).
4. Guaranteed at room temperature.
t
valid_before
t
valid_after
RBC1
1.4 V
2.0 V
RX[0]-RX[9]
K28.5
DATA
DATA
DATA
DATA
0.8 V
2.0 V
BYTSYNC
0.8 V
RBC0
1.4 V
Figure 5. Receiver Section Timing.
t
A-B
DATA BYTE C
DATA BYTE D
± DIN
R5
R6
R7
R8
R9
R0
R1
R2
R3
R4
R5
R6
R7
R8
R9
R2
R3
R4
R5
t_rxlat
RX[0]-RX[9]
DATA BYTE A
DATA BYTE D
RBC1/0
1.4 V
Figure 6. Receiver Latency.
AGILENT [ AGILENT TECHNOLOGIES, LTD. ]
