3
HDMP-1637A Block
Diagram
The HDMP-1637A was designed
to transmit and receive 10-bit
wide parallel data over a single
high-speed line. The parallel data
applied to the transmitter is
expected to be encoded per the
Gigabit Ethernet specification,
which uses an 8B/10B encoding
scheme with special reserve
characters for link management
purposes. In order to accomplish
this task, the HDMP-1637A
incorporates the following:
• TTL Parallel I/Os
• High Speed Phase Locked
Loops
• Parallel to Serial Converter
• Serial Clock and Data
Recovery
• Comma Character Recognition
• Byte Alignment Circuitry
• Serial to Parallel Converter
INPUT LATCH
The transmitter accepts 10-bit
wide TTL parallel data at inputs
TX[0..9]. The user-provided
reference clock signal, REFCLK,
(from this point forward,
REFCLK is defined as the
difference between PECL inputs
+REFCLK and -REFCLK) is used
as the transmit byte clock. The
TX[0..9] and REFCLK signals
must be properly aligned, as
shown in Figure 3.
TX PLL/CLOCK GENERATOR
The transmitter Phase Locked
Loop and Clock Generator (TX
PLL/CLOCK GENERATOR) block
is responsible for generating all
internal clocks needed by the
transmitter section to perform its
functions. These clocks are based
on the supplied reference byte
clock (REFCLK). REFCLK is
used as both the frequency
reference clock for the PLL and
the transmit byte clock for the
incoming data latches. It is
expected to be 125 MHz and
properly aligned to the incoming
parallel data (see Figure 3). This
clock is then multiplied by 10 to
generate the 1250 MHz clock
necessary for clocking the high
speed serial outputs.
FRAME MUX
The FRAME MUX accepts the 10-
bit wide parallel data from the
INPUT LATCH. Using internally
generated high speed clocks, this
parallel data is multiplexed into
the 1250 MBd serial data stream.
The data bits are transmitted
sequentially, from the least
significant bit (TX[0]) to the
most significant bit (TX[9]).
OUTPUT SELECT
The OUTPUT SELECT block
provides for an optional internal
loopback of the high speed serial
signal for testing purposes.
In normal operation, LOOPEN is
set low and the serial data stream
is placed at +/- DOUT. When
wrap-mode is activated by setting
LOOPEN high, the +/- DOUT
pins are held static at logic 1 and
the serial output signal is
internally wrapped to the INPUT
SELECT box of the receiver
section.
INPUT SELECT
The INPUT SELECT block
determines whether the signal at
+/- DIN or the internal loop-back
serial signal is used. In normal
operation, LOOPEN is set low
and the serial data is accepted at
+/- DIN. When LOOPEN is set
high, the high speed serial signal
is internally looped-back from the
transmitter section to the receiver
section. This feature allows for
loop back testing exclusive of the
transmission medium.
RX PLL/CLOCK RECOVERY
The RX PLL/CLOCK RECOVERY
block is responsible for frequency
and phase locking onto the
incoming serial data stream and
recovering the bit and byte
clocks. An automatic locking
feature allows the Rx PLL to lock
onto the input data stream
without external PLL training
controls. It does this by
continually frequency locking
onto the 125 MHz reference
clock, and then phase locking
onto the input data stream. An
internal signal detection circuit
monitors the presence of the
input, and invokes the phase
detection as the data stream
appears. Once bit locked, the
receiver generates the high speed
sampling clock at 1250 MHz for
the input sampler, and recovers
the two 62.5 MHz receiver byte
clocks (RBC1/RBC0). These
clocks are 180 degrees out of
phase with each other, and are
alternately used to clock the 10-
bit parallel output data.
INPUT SAMPLER
The INPUT SAMPLER is
responsible for converting the
serial input signal into a retimed
serial bit stream. In order to
accomplish this, it uses the high
speed serial clock recovered from
the RX PLL/CLOCK RECOVERY
block. This serial bit stream is
sent to the FRAME DEMUX and
BYTE SYNC block.
AGILENT [ AGILENT TECHNOLOGIES, LTD. ]
